公开(公告)号：US06420770B1

公开(公告)日：2002-07-16

申请号：US09882244

申请日：2001-06-15

Applicant: Qi Xiang ,  Wei Long ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC: H01L2900

CPC classification number: H01L29/665 ,  H01L21/76224

Abstract: STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures. The shallow trench isolation structure include a pair of isolation trenches, with each isolation trench being etched through a semiconductor substrate. A first dielectric material fills the pair of isolation trenches and extends from the isolation trenches such that sidewalls of the first dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A second dielectric material is deposited on the sidewalls of the first dielectric material exposed beyond the top of the semiconductor substrate. The second dielectric material has a different etch rate in an acidic solution from the first dielectric material filling the isolation trenches. The present invention may be used to particular advantage when the first dielectric material filling up the isolation trenches is comprised of silicon dioxide, and when the second dielectric material deposited on the sidewalls of the first dielectric material is comprised of silicon nitride. With the protective silicon nitride covering the sidewalls of the silicon dioxide filling the STI (shallow trench isolation) trenches, formation of divots is avoided in the silicon dioxide filling the STI (shallow trench isolation) trenches. Thus, when a field effect transistor is fabricated between such STI structures, silicides formed near the STI structures do not extend down toward the junction of the drain contact region and the source contact region of the field effect transistor such that drain and source leakage current is minimized.

Abstract translation: 制造STI（浅沟槽隔离）结构，使得通过在STI结构之间制造的场效应晶体管使漏电流最小化。 浅沟槽隔离结构包括一对隔离沟槽，每个隔离沟槽通过半导体衬底被蚀刻。 第一介电材料填充一对隔离沟槽并从隔离沟槽延伸，使得填充隔离沟槽的第一介电材料的侧壁暴露在半导体衬底的顶部之外。 第二电介质材料沉积在暴露于半导体衬底的顶部之外的第一电介质材料的侧壁上。 第二电介质材料在从填充隔离沟槽的第一介电材料的酸性溶液中具有不同的蚀刻速率。 当填充隔离沟槽的第一介电材料由二氧化硅组成并且当沉积在第一介电材料的侧壁上的第二介电材料由氮化硅构成时，本发明可以被用于特别有利。 通过覆盖填充STI（浅沟槽隔离）沟槽的二氧化硅的侧壁的保护性氮化硅，在填充STI（浅沟槽隔离）沟槽的二氧化硅中避免形成纹理。 因此，当在这样的STI结构之间制造场效应晶体管时，形成在STI结构附近的硅化物不会朝向场效应晶体管的漏极接触区域和源极接触区域的接点向下延伸，使得漏极和漏极电流为 最小化。

公开(公告)号：US06380019B1

公开(公告)日：2002-04-30

申请号：US09187498

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L2976

CPC classification number: H01L21/74 ,  H01L29/0649 ,  H01L29/6659

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract translation: 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

公开(公告)号：US06281555B1

公开(公告)日：2001-08-28

申请号：US09187861

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01K2976

CPC classification number: H01L21/76237 ,  H01L21/26506 ,  H01L21/2658

Abstract: An integrated circuit is provided having an improved packing density due to an improved isolation structure between a plurality of devices on the substrate. An ultra shallow trench isolation structure is provided, typically having a trench depth just deeper than the doped regions of a transistor or other device placed thereon, but substantially shallower than the depth of a well associated with the transistor. A nitrogen ion implantation step is utilized to fabricate an implanted portion beneath the insulative portion, the implanted portion extending preferably below the depth of the well. Due to a shallower trench isolation structure, the structure may also be narrower, providing for improved packing density in a semiconductor device.

Abstract translation: 提供了一种集成电路，由于衬底上的多个器件之间的改进的隔离结构而具有改进的封装密度。 提供了一种超浅沟槽隔离结构，其通常具有刚好比放置在其上的晶体管或其它器件的掺杂区域更深的沟槽深度，但是基本上比与晶体管相关联的阱的深度浅。 使用氮离子注入步骤来制造在绝缘部分下方的植入部分，所述注入部分优选地延伸到井的深度之下。 由于较浅的沟槽隔离结构，结构也可能更窄，从而提供了半导体器件中改善的封装密度。

公开(公告)号：US06239452B1

公开(公告)日：2001-05-29

申请号：US09320682

申请日：1999-05-27

Applicant: Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

IPC: H01L2184

CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/665

Abstract: A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

Abstract translation: 提供了具有自对准硅化物栅极结构的深亚微米MOS器件及其形成方法，以克服多Si耗尽和硼渗透的问题。 在栅极氧化物和多晶硅栅电极之间形成第一镍硅化物层。 此外，第二镍硅化物层形成在高掺杂源/漏区上。 以这种方式，MOS器件的可靠性将得到提高。

公开(公告)号：US06204138B1

公开(公告)日：2001-03-20

申请号：US09260821

申请日：1999-03-02

Applicant: Srinath Krishnan ,  Witold P. Maszara ,  Ming-Ren Lin

Inventor： Srinath Krishnan ,  Witold P. Maszara ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L29/78612 ,  H01L29/78621

Abstract: A method of forming a MOSFET device is provided. First lightly doped regions are formed, the first lightly doped regions including LDD extension regions of the device. Second very lightly doped regions are formed at least partially below the first lightly doped regions, respectively, the second very lightly doped regions having a dopant concentration less than the first lightly doped regions, and the second very lightly doped regions being implanted at a higher energy level than the first lightly doped regions.

Abstract translation: 提供了一种形成MOSFET器件的方法。 形成第一轻掺杂区域，第一轻掺杂区域包括器件的LDD延伸区域。 第二非常轻掺杂的区域至少部分地形成在第一轻掺杂区域的下方，第二非常轻掺杂的区域具有小于第一轻掺杂区域的掺杂剂浓度，并且第二极轻掺杂区域以较高能量 水平比第一轻掺杂区域。

公开(公告)号：US6077773A

公开(公告)日：2000-06-20

申请号：US974687

申请日：1997-11-19

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

Abstract: Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric material in the opening.

Abstract translation: 通过形成具有初始尺寸的开口并通过在开口中沉积第二介电材料来减小初始尺寸，在介电层中提供亚微米触点/通孔和沟槽。

公开(公告)号：US5863707A

公开(公告)日：1999-01-26

申请号：US798992

申请日：1997-02-11

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: G03F7/00 ,  G03F7/40 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  G03C5/00

CPC classification number: H01L21/32139 ,  G03F7/00 ,  G03F7/40 ,  H01L21/0338 ,  H01L21/76816 ,  H01L21/31144

Abstract: Sub-micron contacts/vias and conductive lines in a dielectric layer are formed by etching through a photoresist mask containing openings having a dimension less than that achievable by conventional photolithographic techniques. Such minimal size openings are obtained by initially forming an oversized opening by conventional photolithographic techniques and then reducing the size of the opening by forming a sidewall spacer, such as a dielectric sidewall spacer, within the opening. In an embodiment, a plurality of openings are formed in first photoresist layer, each of which openings is provided with a sidewall spacer. The openings are filled with a filling material, such as a second photoresist material, and the photoresist mask and sidewall spacers are removed leaving a plurality of masking portions containing the second photoresist material. An underlying conductive layer is then etched through masking portions to form conductive lines having sub-micron dimensions.

Abstract translation: 通过蚀刻通过含有小于通过常规光刻技术可实现的尺寸的开口的光致抗蚀剂掩模来形成介电层中的亚微米触点/通孔和导电线。 通过最初通过常规光刻技术形成尺寸过大的开口，然后通过在开口内形成侧壁间隔物（例如电介质侧壁间隔物）来减小开口的尺寸来获得这种最小尺寸的开口。 在一个实施例中，在第一光致抗蚀剂层中形成多个开口，每个开口设置有侧壁间隔物。 开口填充有诸如第二光致抗蚀剂材料的填充材料，并且除去光致抗蚀剂掩模和侧壁间隔物，留下包含第二光致抗蚀剂材料的多个掩模部分。 然后通过掩模部分蚀刻底层导电层，以形成具有亚微米尺寸的导电线。

公开(公告)号：US5795823A

公开(公告)日：1998-08-18

申请号：US752807

申请日：1996-11-20

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L21/441

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1036 ,  H01L2924/0002

Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.

Abstract translation: 一种用于集成电路和用于半导体器件的衬底载体的绝缘体分隔开的导线的连接通孔和通孔的方法，其中使用双镶嵌仅具有一个用于形成导电线和通孔的掩​​模图案。 导电线的掩模图案包含​​在绝缘材料中要形成通孔开口的横向扩大区域。 在产生具有横向扩大区域的导电线路开口之后，开口用适形材料填充，其保护材料的蚀刻选择性基本上小于绝缘材料对用于蚀刻绝缘材料的附魔的蚀刻选择性，并且其蚀刻选择性基本上大于 绝缘材料到其附魔。 保形材料被各向异性地蚀刻以在扩大区域中形成侧壁并且移除侧壁之间的材料，而留下留在导电线开口部分中的材料。 侧壁用作通过开口蚀刻的自对准掩模。 保形材料是导电材料，其在形成通孔开口之后留在适当位置或者被去除的绝缘材料。 在前者中，部分填充的导电线路开口与另外的导电材料一起填充，该通孔是相同或不同的导电材料。 在后者中，导电线路开口和通孔用相同的导电材料填充。

公开(公告)号：US5785236A

公开(公告)日：1998-07-28

申请号：US564695

申请日：1995-11-29

Applicant: Robin W. Cheung ,  Ming-Ren Lin

Inventor： Robin W. Cheung ,  Ming-Ren Lin

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/05 ,  H01L23/5283 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L24/45 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/49204

Abstract: A process is provided which enables electrical connection to be formed between gold and aluminum wires and copper interconnects. Conventional techniques for wire bonding are ineffective for bonding gold wires or aluminum wires to copper pads or copper interconnects. A process is provided to modify the copper pads so that conventional wire bonding techniques can be employed. In the process of the present invention an aluminum pad is formed over the copper interconnects. The metal wire is then bonded to the aluminum pad using conventional wire bonding techniques. No new hardware and/or technology is required for the metal wire bonding. No new technology is required to integrate the process of the invention into existing IC fabrication processes.

Abstract translation: 提供一种能够在金和铝线和铜互连之间形成电连接的工艺。 用于引线接合的常规技术对于将金线或铝线接合到铜焊盘或铜互连无效。 提供了一种修改铜焊盘的工艺，以便可以采用常规的引线接合技术。 在本发明的方法中，在铜互连件上形成铝焊盘。 然后使用常规的引线接合技术将金属线接合到铝焊盘。 金属线接合不需要新的硬件和/或技术。 将本发明的方法整合到现有的IC制造工艺中不需要新的技术。

公开(公告)号：US5705430A

公开(公告)日：1998-01-06

申请号：US486777

申请日：1995-06-07

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76808 ,  H01L2221/1031

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a sacrificial via fill. A first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is deposed on the first layer. In one embodiment, the etch selectivity to the etchant of the second layer is essentially the same as the sacrificial via fill and, preferably, is substantially higher than second layer. Using a conductive line pattern aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings. In a second embodiment, the sacrificial material is not etchable by the etchant for forming the conductive line openings and, after formation of the conductive line openings, the sacrificial material is removed with an etchant to which the first insulating layer is resistive or less selective. A conductive material now is deposited in the conductive line and via openings.

Abstract translation: 一种双镶嵌方法，用于制造用于集成电路的绝缘体分隔开的导电线路的互连电平和用于半导体器件的衬底载体的通孔，其使用牺牲通孔填充物。 第一层绝缘材料形成有通孔。 开口填充有牺牲可移除材料。 在第一层上放置第二层绝缘材料。 在一个实施例中，对第二层的蚀刻剂的蚀刻选择性基本上与牺牲通孔填充相同，并且优选地基本上高于第二层。 使用与通孔开口对准的导电线图案，在第二绝缘层中蚀刻导电线开口，并且在蚀刻期间，将牺牲填充物从通孔开口移除。 在第二实施例中，牺牲材料不可蚀刻用于形成导电线路开口的蚀刻剂，并且在形成导电线路开口之后，用第一绝缘层具有电阻或较小选择性的蚀刻剂去除牺牲材料。 导电材料现在沉积在导电线和通孔中。