公开(公告)号：US07542018B2

公开(公告)日：2009-06-02

申请号：US11861494

申请日：2007-09-26

申请人： Aya Anzai ,  Mitsuaki Osame ,  Yoshifumi Tanada ,  Keisuke Miyagawa ,  Satoshi Seo ,  Shunpei Yamazaki

发明人： Aya Anzai ,  Mitsuaki Osame ,  Yoshifumi Tanada ,  Keisuke Miyagawa ,  Satoshi Seo ,  Shunpei Yamazaki

IPC分类号： G09G3/30

CPC分类号： G09G3/3266 ,  G09G3/2022 ,  G09G3/3258 ,  G09G3/3291 ,  G09G3/3655 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2300/0847 ,  G09G2300/0866 ,  G09G2310/0251 ,  G09G2310/0256 ,  G09G2310/0262 ,  G09G2310/027 ,  G09G2310/0278 ,  G09G2320/043 ,  G09G2330/021 ,  H01L27/3244

摘要： The reliability of an EL element is enhanced while the increase of the electric power consumption is suppressed. It becomes possible that in a SES drive, the reverse bias is applied to the EL element driven at a constant electric current. Moreover, the application of the reverse bias is performed by varying only the counter electrode, and thus withstand voltage of TFT and the increase of the electric power consumption due to the increase of voltage of the gate signal line drive circuit, which becomes a problem when changing greatly the electric current supplying line, can be suppressed. Furthermore, the reduction of the electric power consumption can also be achieved while the enhancement of the reliability is secured by making the reverse bias smaller than the forward bias. Moreover, the increase of the number of electric sources can be also suppressed by making the potential be in common with the potential of the electric source of the source signal line drive circuit or the gate signal line drive circuit, at the time when the reverse bias is applied.

公开(公告)号：US20090051630A1

公开(公告)日：2009-02-26

申请号：US12257990

申请日：2008-10-24

申请人： Mitsuaki Osame ,  Aya Anzai

发明人： Mitsuaki Osame ,  Aya Anzai

IPC分类号： G09G3/32 ,  H04B1/38 ,  H04M1/00 ,  G06F17/00

CPC分类号： G09G3/3208 ,  G09G3/3216 ,  G09G3/3225 ,  G09G2320/029 ,  G09G2320/041 ,  G09G2320/043 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2330/08

摘要： The invention has a monitoring portion which detects change of ambient temperature and degradation with time, provided with a plurality of monitoring pixels and a monitoring line. Each of the plurality of monitoring pixels has a light emitting element for monitoring, a constant current source, a switch, and a detecting circuit, and one electrode of the light emitting element for monitoring is connected to the monitoring line through the switch. The detecting circuit controls on and off of the switch, and specifically in the case where both electrodes of the light emitting element for monitoring are short-circuited, the switch is turned off. The invention having the aforementioned configuration generates no potential change of the power supply line of the pixel portion when both electrodes of a light emitting element for monitoring are short-circuited.

摘要翻译： 本发明具有检测环境温度的变化和随着时间的劣化的监视部分，设置有多个监视像素和监视线。 多个监视像素中的每一个具有用于监视的发光元件，恒流源，开关和检测电路，用于监视的发光元件的一个电极通过开关连接到监视线。 检测电路控制开关的导通和关断，特别是在用于监视的发光元件的两个电极短路的情况下，开关被断开。 具有上述构造的本发明当用于监视的发光元件的两个电极短路时，不产生像素部分的电源线的电位变化。

公开(公告)号：US07327169B2

公开(公告)日：2008-02-05

申请号：US10668247

申请日：2003-09-24

申请人： Mitsuaki Osame ,  Aya Anzai

发明人： Mitsuaki Osame ,  Aya Anzai

IPC分类号： H03K19/20

CPC分类号： H03K19/018521 ,  G11C19/00 ,  G11C19/28 ,  H03K19/00384 ,  H03K19/0963

摘要： A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series. In the clocked inverter, gates of the third transistor and the fourth transistor are connected to each other, drains of the third transistor and the fourth transistor are each connected to a gate of the first transistor, sources of the first transistor and the fourth transistor are each electrically connected to a first power source, a source of the second transistor is electrically connected to a second power source, and an amplitude of a signal inputted to a source of the third transistor is smaller than a potential difference between the first power source and the second power source.

摘要翻译： 晶体管的阈值电压由于栅极绝缘膜的膜厚的波动或由于使用的衬底的差异或制造步骤引起的栅极长度和栅极宽度而波动。 为了解决该问题，根据本发明，提供了一种包括串联连接的第一晶体管和第二晶体管的时钟反相器，以及包括串联连接的第三晶体管和第四晶体管的补偿电路。 在时钟反相器中，第三晶体管和第四晶体管的栅极彼此连接，第三晶体管和第四晶体管的漏极分别连接到第一晶体管的栅极，第一晶体管和第四晶体管的源极 每个电连接到第一电源，第二晶体管的源极电连接到第二电源，并且输入到第三晶体管的源极的信号的幅度小于第一电源和第二电源之间的电位差， 第二个电源。

公开(公告)号：US07142030B2

公开(公告)日：2006-11-28

申请号：US10724365

申请日：2003-12-01

申请人： Mitsuaki Osame ,  Aya Anzai

发明人： Mitsuaki Osame ,  Aya Anzai

IPC分类号： H03K3/12

CPC分类号： H03K5/249 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3291 ,  G09G3/3648 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2320/0233 ,  G11C19/184 ,  H03K3/356121

摘要： The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the other electrode of the capacitor, an accurate operation can be obtained without being influenced by variations in the TFT characteristics even when the amplitude of an input signal is small relatively to the width of a power supply voltage.

摘要翻译： 本发明的数据锁存电路包括用于使逆变器的输入端子和输出端子短路的装置，并且将输入端子连接到电容器的一个电极，并将数据信号或参考电位采样到另一个电极的另一个电极 即使当输入信号的幅度相对于电源电压的宽度较小时，也可以不受TFT特性的变化的影响而获得精确的操作。

公开(公告)号：US20060118699A1

公开(公告)日：2006-06-08

申请号：US11292058

申请日：2005-12-02

申请人： Mitsuaki Osame ,  Aya Anzai

发明人： Mitsuaki Osame ,  Aya Anzai

IPC分类号： H01L31/00

CPC分类号： G09G3/3208 ,  G09G3/3216 ,  G09G3/3225 ,  G09G2320/029 ,  G09G2320/041 ,  G09G2320/043 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2330/08

摘要： The invention has a monitoring portion which detects change of ambient temperature and degradation with time, provided with a plurality of monitoring pixels and a monitoring line. Each of the plurality of monitoring pixels has a light emitting element for monitoring, a constant current source, a switch, and a detecting circuit, and one electrode of the light emitting element for monitoring is connected to the monitoring line through the switch. The detecting circuit controls on and off of the switch, and specifically in the case where both electrodes of the light emitting element for monitoring are short-circuited, the switch is turned off. The invention having the aforementioned configuration generates no potential change of the power supply line of the pixel portion when both electrodes of a light emitting element for monitoring are short-circuited.

摘要翻译： 本发明具有检测环境温度的变化和随时间劣化的监视部分，设置有多个监视像素和监视线。 多个监视像素中的每一个具有用于监视的发光元件，恒流源，开关和检测电路，用于监视的发光元件的一个电极通过开关连接到监视线。 检测电路控制开关的导通和关断，特别是在用于监视的发光元件的两个电极短路的情况下，开关被断开。 具有上述构造的本发明当用于监视的发光元件的两个电极短路时，不产生像素部分的电源线的电位变化。

公开(公告)号：US08432385B2

公开(公告)日：2013-04-30

申请号：US13271584

申请日：2011-10-12

申请人： Mitsuaki Osame ,  Aya Anzai

发明人： Mitsuaki Osame ,  Aya Anzai

IPC分类号： G09G5/00 ,  G09G3/20

CPC分类号： H03K19/018521 ,  G11C19/00 ,  G11C19/28 ,  H03K19/00384 ,  H03K19/0963

摘要： In a display device including a substrate, a pixel portion, and a driver circuit having first to ninth transistors and first and second inverters, the various transistors are configured such that one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor. In embodiments, the electrical connection may be a direct connection. Additionally, a switch may be provided that is directly connected to an output terminal of the second inverter.

摘要翻译： 在包括基板，像素部分和具有第一至第九晶体管和第一和第二反相器的驱动器电路的显示装置中，各种晶体管被配置为使得第五晶体管的源极和漏极中的一个电连接到 第一晶体管的栅极。 在实施例中，电连接可以是直接连接。 另外，可以提供直接连接到第二反相器的输出端的开关。

公开(公告)号：US08189733B2

公开(公告)日：2012-05-29

申请号：US12704766

申请日：2010-02-12

申请人： Mitsuaki Osame ,  Aya Anzai

发明人： Mitsuaki Osame ,  Aya Anzai

IPC分类号： G11C19/00

CPC分类号： H03K5/249 ,  G11C19/00 ,  G11C19/184 ,  H03K5/003 ,  H03K5/02 ,  H03K5/082

摘要： A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this mariner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided.

摘要翻译： 低功耗移位寄存器，其输入具有低电压的CK信号，几乎不影响晶体管的特性变化。 在本发明中，将逆变器的输入部设定为阈值电压，通过电容器装置将CK信号输入到逆变器的输入部。 在这个水手中，CK信号被放大，发送到移位寄存器。 也就是说，通过获得反相器的阈值电位，可以提供几乎不影响晶体管特性变化的移位寄存器。 可以从移位寄存器的输出脉冲产生CK信号的电平移位器，因此可以提供具有短时间流过直通电流的电平移位器的低功耗移位寄存器。

公开(公告)号：US20110304605A1

公开(公告)日：2011-12-15

申请号：US13213483

申请日：2011-08-19

申请人： Mitsuaki Osame ,  Aya Anzai

发明人： Mitsuaki Osame ,  Aya Anzai

IPC分类号： G09G5/00

CPC分类号： H03K5/249 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3291 ,  G09G3/3648 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2320/0233 ,  G11C19/184 ,  H03K3/356121

摘要： The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the other electrode of the capacitor, an accurate operation can be obtained without being influenced by variations in the TFT characteristics even when the amplitude of an input signal is small relatively to the width of a power supply voltage.

摘要翻译： 本发明的数据锁存电路包括用于使逆变器的输入端子和输出端子短路的装置，并且将输入端子连接到电容器的一个电极，并将数据信号或参考电位采样到另一个电极的另一个电极 即使当输入信号的幅度相对于电源电压的宽度较小时，也可以不受TFT特性的变化的影响而获得精确的操作。

公开(公告)号：US20110187762A1

公开(公告)日：2011-08-04

申请号：US13085521

申请日：2011-04-13

申请人： Mitsuaki Osame ,  Aya Anzai

发明人： Mitsuaki Osame ,  Aya Anzai

IPC分类号： G09G5/10

CPC分类号： G09G3/3258 ,  G09G3/2022 ,  G09G2300/0857 ,  G09G2310/0251 ,  G09G2320/0223 ,  G09G2330/023

摘要： A semiconductor device of the invention includes a data line, a power source line, a first scan line, a second scan line, a first transistor, a second transistor, a memory circuit, a third transistor, and a light-emitting element. A gate of the first transistor is connected to the data line, and a first terminal thereof is connected to the power source line; a gate of the second transistor is connected to the first scan line, and a first terminal thereof is connected to a second terminal of the first transistor; the memory circuit is connected to a second terminal of the second transistor and the second scan line; a first terminal of the third transistor is connected to the light-emitting element; and the memory circuit holds a first potential inputted from the power source line or a second potential inputted from the second scan line, and applies the potential to a gate of the third transistor to control emission/non-emission of the light-emitting element.

摘要翻译： 本发明的半导体器件包括数据线，电源线，第一扫描线，第二扫描线，第一晶体管，第二晶体管，存储电路，第三晶体管和发光元件。 第一晶体管的栅极连接到数据线，其第一端连接到电源线; 第二晶体管的栅极连接到第一扫描线，其第一端连接到第一晶体管的第二端; 存储电路连接到第二晶体管和第二扫描线的第二端子; 第三晶体管的第一端子连接到发光元件; 并且存储电路保持从电源线输入的第一电位或从第二扫描线输入的第二电位，并且将电位施加到第三晶体管的栅极以控制发光元件的发射/不发光。

公开(公告)号：US07843217B2

公开(公告)日：2010-11-30

申请号：US12565796

申请日：2009-09-24

申请人： Mitsuaki Osame ,  Aya Anzai

发明人： Mitsuaki Osame ,  Aya Anzai

IPC分类号： H03K19/173 ,  H03K5/153 ,  H03K3/01 ,  G05F1/10

CPC分类号： G09G3/3677 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3688 ,  G11C19/00 ,  G11C19/28

摘要： The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

摘要翻译： 本发明提供了一种能够在抑制信号延迟和波形舍入的同时正常工作的移位寄存器。 本发明的移位寄存器包括多个级的触发器电路，每个触发器电路包括时钟反相器。 时钟反相器包括串联连接的第一晶体管和第二晶体管，包括串联连接的第三晶体管和第四晶体管的第一补偿电路和包括第五晶体管和透射栅的第二补偿电路。 根据第一补偿电路，可以与前两级的输出同步地控制从触发器电路输出的信号上升或下降的定时。 第二补偿电路可以控制时钟信号输入可以控制。