公开(公告)号：US06773337B1

公开(公告)日：2004-08-10

申请号：US09993809

申请日：2001-11-06

申请人： Sanjay Dabral ,  Anil K. Pant

发明人： Sanjay Dabral ,  Anil K. Pant

IPC分类号： B24B100

CPC分类号： B24B53/017 ,  B24B37/042 ,  B24D3/344 ,  B24D7/02

摘要： In certain embodiments of the invention an ion exchange polish pad, which is used for polishing Copper layers formed on a semiconductor substrate, may be conditioned and/or reconditioned to regenerate its binding capacity for cations. Once bound to an ion exchange polish pad, cations for example may be exchanged for protons (H+) by exposing the ion exchange polish pad to a reconditioning medium(s). The exchange of cations with H+ reconditions the ion exchange material of an ion exchange polish pad so it is capable of binding and removing additional cations from a surface. In certain embodiments, a reconditioning head is used to recondition an ion exchange polish pad. A typical reconditioning process comprises elution of bound copper from ion exchange polish pad followed by protonation. Elution of bound copper may be accomplished by exposing an ion exchange polish pad to a strong acid solution, or similar chemical treatments.

摘要翻译： 在本发明的某些实施方案中，用于抛光形成在半导体衬底上的铜层的离子交换抛光垫可以被调理和/或再生以再生其对阳离子的结合能力。 一旦结合到离子交换抛光垫上，阳离子例如可以通过将离子交换抛光垫暴露于修复介质来交换质子（H +）。 用H +交换阳离子重新调整离子交换抛光垫的离子交换材料，使其能够从表面结合和除去附加的阳离子。 在某些实施例中，使用修复头来重新调整离子交换抛光垫。 典型的修复方法包括从离子交换抛光垫洗脱结合的铜，然后质子化。 结合铜的洗脱可以通过将离子交换抛光垫暴露于强酸溶液或类似的化学处理来实现。

公开(公告)号：US06722950B1

公开(公告)日：2004-04-20

申请号：US09993807

申请日：2001-11-06

申请人： Sanjay Dabral ,  Anil K. Pant

发明人： Sanjay Dabral ,  Anil K. Pant

IPC分类号： B24B100

CPC分类号： B24B53/017 ,  B23H5/08 ,  B24B37/042 ,  B24B37/046 ,  B24D3/344 ,  B24D7/02 ,  H01L21/32125 ,  H01L21/7684 ,  Y10S451/908

摘要： Embodiments of the invention include methods and apparatus for electrodialytic polishing of various layers formed on semiconductor substrates. In certain embodiments the use of electrodialytic processes in conjunction with chemical mechanical forces to achieve a copper interconnect with a desired level of planarity and process performance. In certain embodiments electrodialytic polishing uses an electrodialytic polish pad, which is an active pad which has copper binding groups provided in its core structure and has an added capability of allowing electrical conductivity. An electrodialytic polish pad allows transfer of cations or anions through a membrane in the presence of an electric field and into a cathodic electrolyte. Under the influence of an electric field the electrodialytic polish pad and/or electrodialytic pads are continuously refreshed to bind cations.

摘要翻译： 本发明的实施例包括用于在半导体衬底上形成的各种层的电渗析的方法和装置。 在某些实施方案中，使用电渗析方法结合化学机械力来实现具有期望水平的平面性和工艺性能的铜互连。 在某些实施方案中，电渗析抛光使用电渗析抛光垫，其为具有在其核心结构中提供的铜结合基团并具有允许导电性的附加能力的活性垫。 电渗透抛光垫允许阳离子或阴离子在电场存在下通过膜转移到阴极电解质中。 在电场的影响下，电渗析抛光垫和/或电渗析垫不断刷新以结合阳离子。

公开(公告)号：US06715111B2

公开(公告)日：2004-03-30

申请号：US09748233

申请日：2000-12-27

申请人： Keith Self ,  Michael Sandhinti ,  Sanjay Dabral

发明人： Keith Self ,  Michael Sandhinti ,  Sanjay Dabral

IPC分类号： G06F1100

CPC分类号： G06F11/0745 ,  G06F11/076

摘要： A method and apparatus for detecting data strobe errors. A strobe error detection circuit has a strobe input and a counter coupled to the strobe input to count strobe pulses received. The circuit also has a comparator to determine if a strobe error has occurred based on the magnitude of the difference between a first count of strobe pulses and a second count of strobe pulses. In an embodiment, the first count is read from a memory location at a first time and the second count is read at a second time.

摘要翻译： 一种用于检测数据选通错误的方法和装置。 选通错误检测电路具有选通输入和耦合到选通输入的计数器以对接收到的选通脉冲进行计数。 该电路还具有一个比较器，用于根据第一次选通脉冲计数和第二个选通脉冲计数之间的差值的大小来确定是否发生了选通脉冲错误。 在一个实施例中，在第一时间从存储器位置读取第一计数，并且在第二时间读取第二计数。

公开(公告)号：US06661277B2

公开(公告)日：2003-12-09

申请号：US10314309

申请日：2002-12-09

申请人： Sanjay Dabral

发明人： Sanjay Dabral

IPC分类号： H03K301

CPC分类号： H03K19/0027 ,  H01L29/78 ,  H03K2217/0018

摘要： According to one embodiment of the present invention a method for biasing a body of a transistor. The method includes detecting a voltage applied to a terminal of a transistor and coupling a biasing voltage to the body based upon the detected voltage.

摘要翻译： 根据本发明的一个实施例，一种用于偏置晶体管本体的方法。 该方法包括检测施加到晶体管的端子的电压，并且基于检测到的电压将偏置电压耦合到身体。

公开(公告)号：US06622256B1

公开(公告)日：2003-09-16

申请号：US09539666

申请日：2000-03-30

申请人： Sanjay Dabral ,  Alper Ilkbahar

发明人： Sanjay Dabral ,  Alper Ilkbahar

IPC分类号： G06F104

CPC分类号： H03K5/1252 ,  H03K5/133 ,  H03L7/0805 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/005

摘要： A method and apparatus for a strobe glitch protection mechanism for a source synchronous I/O link. One method of the present invention comprises separating a transfer clock having a plurality of transfer clock edges into a pointer path and a timing path. Glitches are filtered from signals on said pointer path. The pointer path and the timing path are coupled to generate latch enable signals to latch data bits.

摘要翻译： 一种用于源同步I / O链路的选通脉冲干扰保护机制的方法和装置。 本发明的一种方法包括将具有多个传送时钟边缘的传送时钟分离成指针路径和定时路径。 毛刺从所述指针路径上的信号中滤除。 指针路径和定时路径被耦合以产生锁存使能信号以锁存数据位。

公开(公告)号：US06601196B1

公开(公告)日：2003-07-29

申请号：US09608449

申请日：2000-06-29

申请人： Sanjay Dabral ,  Ramesh Senthinathan ,  Ming Zeng ,  Keith Self ,  Ernest Khaw ,  Chung-Wai Yue

发明人： Sanjay Dabral ,  Ramesh Senthinathan ,  Ming Zeng ,  Keith Self ,  Ernest Khaw ,  Chung-Wai Yue

IPC分类号： G06F1100

CPC分类号： G06F11/221

摘要： An apparatus and method for debugging a bus including interposing a device that monitors the data transferred between two devices on the bus such that the bus is split into two busses, with data being copied for transmission to a diagnostics device as the data is transferred between the two busses.

摘要翻译： 一种用于调试总线的装置和方法，包括插入监视总线上的两个设备之间传输的数据的设备，使得总线被分成两个总线，当数据被复制以传输到诊断设备时，数据在 两辆巴士。

公开(公告)号：US06515534B2

公开(公告)日：2003-02-04

申请号：US09475648

申请日：1999-12-30

申请人： Sanjay Dabral

发明人： Sanjay Dabral

IPC分类号： H03K301

CPC分类号： H03K19/0027 ,  H01L29/78 ,  H03K2217/0018

摘要： According to one embodiment of the present invention a method for biasing a body of a transistor. The method includes detecting a voltage applied to a terminal of a transistor and coupling a biasing voltage to the body based upon the detected voltage.

公开(公告)号：US6137143A

公开(公告)日：2000-10-24

申请号：US107351

申请日：1998-06-30

申请人： Sanjay Dabral ,  Krishna Seshan

发明人： Sanjay Dabral ,  Krishna Seshan

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0255 ,  H01L2924/0002

摘要： An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

摘要翻译： 一种集成电路，其包括占用集成电路基板的第一区域的性能电路和耦合到所述性能电路并且占据与所述第一区域分离的集成电路基板的第二区域的保护电路。 此外，形成集成电路的方法包括以下步骤：形成占据集成电路基板的第一区域的性能电路，形成与第一区域分离的占据集成电路的第二区域的保护电路，以及耦合保护 电路到性能电路。

公开(公告)号：US5781258A

公开(公告)日：1998-07-14

申请号：US662618

申请日：1996-06-13

申请人： Sanjay Dabral ,  Raymond G. Greene ,  John P. Koons ,  Donald P. Seraphim ,  Boris Yost

发明人： Sanjay Dabral ,  Raymond G. Greene ,  John P. Koons ,  Donald P. Seraphim ,  Boris Yost

IPC分类号： G02F1/1333 ,  G02F1/1339 ,  G02F1/133

CPC分类号： G02F1/1339 ,  G02F1/13336

摘要： The present invention features flat-panel displays having a mosaic of tiles, and methods of constructing and sealing them. Sealing designs are described to maintain appropriate vacuum levels for FEDs, PFPDs and LCDs. The mosaic of tiles forming a flat-panel display may include subassembly tiles, with each consisting of two, unsealed, substantially parallel plates having a structure positioned between them; these are known as s-tiles. The tiles may be enclosed by a cover plate and backplate. Non-permeable material may be deposited on the cover plate and the backplate, with solderable metal overlaid on the non-permeable material. A metallized, non-permeable spacer/connector is also located between the cover plate and backplate for hermetically sealing the perimeter of the display. A set of electrical-interconnection, metal feed-throughs can also be positioned in the non-permeable spacer/connector. A flat-panel display may also be made up of half-tiles (h-tiles), with each including an individual bottom plate with a structure disposed on them. The mosaic of tiles also has a cover plate that is shared in common with all of the h-tiles. This common cover plate for each type of FPD integrates functions such as masking, screening, color filtering, polarizing and interconnecting. Also provided in the invention is a method for testing the seal of the flat-panel display. A simulated cover plate is attached via a polymeric seal, so that a structure enclosed between the two plates may be evacuated. When a gas is applied around the display seal, its leakage rate is measured, so as to locate the site of defects.

摘要翻译： 本发明的特征在于具有瓦片马赛克的平板显示器，以及构造和密封它们的方法。 描述了密封设计，以保持FED，PFPD和LCD的适当真空度。 形成平板显示器的瓷砖的马赛克可以包括子组件瓦片，每个瓦片包括两个未密封的基本平行的板，其具有位于它们之间的结构; 这些被称为s-tiles。 瓦片可以由盖板和背板封闭。 不可渗透的材料可以沉积在盖板和背板上，可焊接的金属覆盖在不可渗透的材料上。 金属化的，不可渗透的间隔件/连接器也位于盖板和背板之间，用于气密地密封显示器的周边。 一组电互连，金属馈通也可以定位在不可渗透的间隔件/连接器中。 平板显示器也可以由半瓦片（h瓦片）组成，每个瓦片包括设置在其上的结构的单个底板。 瓷砖的马赛克还具有与所有h瓦片共享的盖板。 这种用于每种类型的FPD的普通盖板集成了诸如掩模，筛选，滤色，偏振和互连的功能。 本发明还提供了一种用于测试平板显示器的密封件的方法。 模拟盖板通过聚合物密封件连接，使得封闭在两个板之间的结构可以被抽空。 当在显示器密封件周围施加气体时，测量其泄漏率，以便定位缺陷位置。

公开(公告)号：US08315347B2

公开(公告)日：2012-11-20

申请号：US12592705

申请日：2009-12-01

申请人： Karthisha S. Canagasaby ,  Sanjay Dabral

发明人： Karthisha S. Canagasaby ,  Sanjay Dabral

IPC分类号： H04L7/02

CPC分类号： H04L7/0054 ,  H04L7/0025 ,  H04L7/0337

摘要： An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.

摘要翻译： 电子通信接收机包括导出的时钟信号电路，其可操作以接收数据信号并从接收的数据信号导出导出的时钟信号。 单独转发的时钟信号电路还可操作以接收转发的时钟信号，并且时钟管理电路可操作以从导出的时钟信号电路和转发的时钟信号电路接收信号，并输出输出时钟信号。