公开(公告)号：US6043682A

公开(公告)日：2000-03-28

申请号：US997223

申请日：1997-12-23

申请人： Sanjay Dabral ,  Dilip K. Sampath ,  Alper Ilkbahar

发明人： Sanjay Dabral ,  Dilip K. Sampath ,  Alper Ilkbahar

IPC分类号： H03K19/003 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/00361

摘要： A buffer for enabling a signal to be applied to a bus. The buffer includes a first transistor coupled to a bus and a voltage supply. The logic buffer includes a first logic circuit which has an input coupled to receive a data signal and adapted to charge a terminal of the transistor at a first rate in response to a transition in the data signal. A second logic circuit charges the terminal at a faster rate during an initial transition period, until a first preselected condition is met. The buffer also includes a third logic circuit to charge the terminal at a second faster rate during a final transition period, after a second preselected condition is met. A method for controlling a voltage level of a signal applied to a terminal of a transistor includes charging the terminal at a fast rate until a first preselected condition is met. The terminal is then charged at a slower rate, until a second preselected condition is met, at which time the terminal is charged at a second fast rate, which is also greater than the slower rate.

摘要翻译： 用于使信号施加到总线的缓冲器。 缓冲器包括耦合到总线的第一晶体管和电压源。 逻辑缓冲器包括第一逻辑电路，其具有耦合以接收数据信号的输入，并且适于响应于数据信号中的转变以第一速率对晶体管的端子充电。 第二逻辑电路在初始过渡期间以更快的速率对终端充电，直到满足第一预选条件。 缓冲器还包括第三逻辑电路，以在满足第二预选条件之后，在最后的过渡期期间以更快的速率对终端充电。 用于控制施加到晶体管的端子的信号的电压电平的方法包括以快速的速率对端子充电直到满足第一预选条件。 然后以较慢的速率对终端进行充电，直到满足第二预选条件，此时终端以第二快速率充电，其也大于较慢速率。

公开(公告)号：US6154498A

公开(公告)日：2000-11-28

申请号：US938359

申请日：1997-09-26

申请人： Sanjay Dabral ,  Dilip K. Sampath ,  Alper Ilkbahar

发明人： Sanjay Dabral ,  Dilip K. Sampath ,  Alper Ilkbahar

IPC分类号： G06F13/40 ,  H04L25/06 ,  H04L25/08 ,  H04B3/00 ,  H03K3/00 ,  H04L23/00 ,  H04L27/00

CPC分类号： G06F13/4072 ,  H04L25/06 ,  H04L25/085

摘要： A computer system with a semi-differential bus-signaling scheme is described. The computer system includes a transmitter coupled to a common bus. The transmitter sends clock signals and a data signal to logic-comparing devices within a receiver. The logic-comparing devices compare the data signal to a reference voltage while comparing the clock signals to each other. After the comparison, the clock signals can be used to capture the data into a retiming circuit.

摘要翻译： 描述了具有半差分总线信令方案的计算机系统。 计算机系统包括耦合到公共总线的发射器。 发射机将时钟信号和数据信号发送到接收机内的逻辑比较装置。 逻辑比较器件将数据信号与参考电压进行比较，同时将时钟信号彼此进行比较。 比较后，可以使用时钟信号将数据捕获到重新定时电路中。

公开(公告)号：US06622256B1

公开(公告)日：2003-09-16

申请号：US09539666

申请日：2000-03-30

申请人： Sanjay Dabral ,  Alper Ilkbahar

发明人： Sanjay Dabral ,  Alper Ilkbahar

IPC分类号： G06F104

CPC分类号： H03K5/1252 ,  H03K5/133 ,  H03L7/0805 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/005

摘要： A method and apparatus for a strobe glitch protection mechanism for a source synchronous I/O link. One method of the present invention comprises separating a transfer clock having a plurality of transfer clock edges into a pointer path and a timing path. Glitches are filtered from signals on said pointer path. The pointer path and the timing path are coupled to generate latch enable signals to latch data bits.

摘要翻译： 一种用于源同步I / O链路的选通脉冲干扰保护机制的方法和装置。 本发明的一种方法包括将具有多个传送时钟边缘的传送时钟分离成指针路径和定时路径。 毛刺从所述指针路径上的信号中滤除。 指针路径和定时路径被耦合以产生锁存使能信号以锁存数据位。

公开(公告)号：US08659028B2

公开(公告)日：2014-02-25

申请号：US11764789

申请日：2007-06-18

申请人： Roy E. Scheuerlein ,  Alper Ilkbahar ,  Luca G. Fasoli

发明人： Roy E. Scheuerlein ,  Alper Ilkbahar ,  Luca G. Fasoli

IPC分类号： H01L27/10

CPC分类号： G11C7/18 ,  G11C16/0416 ,  G11C16/0466 ,  G11C17/12 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/77 ,  Y10S257/91

摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

公开(公告)号：US07433233B2

公开(公告)日：2008-10-07

申请号：US11764793

申请日：2007-06-18

申请人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

发明人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1159

摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

公开(公告)号：US06940109B2

公开(公告)日：2005-09-06

申请号：US10779760

申请日：2004-02-18

申请人： Kedar Patel ,  Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew J. Walker

发明人： Kedar Patel ,  Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew J. Walker

IPC分类号： H01L21/8239 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L29/76

CPC分类号： H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052

摘要： A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.

摘要翻译： 半导体器件包括两个晶体管，其中一个晶体管的栅电极和另一个晶体管的源极或漏极位于同一导轨中。 单片三维阵列包含多个这样的装置。 阵列的不同级别的晶体管优选地具有不同的取向。

公开(公告)号：US06528380B2

公开(公告)日：2003-03-04

申请号：US09895509

申请日：2001-06-29

申请人： Bruce Woolery ,  Alper Ilkbahar

发明人： Bruce Woolery ,  Alper Ilkbahar

IPC分类号： H01L218222

CPC分类号： H01L27/0629 ,  H01L27/0288

摘要： An n-well resistor device and its method of fabrication. The n-well resistor device of the present invention comprises a first n-type region and a second n-type region formed in an n-type silicon region. A gate dielectric layer formed on said n-type silicon region. A polysilicon gate formed on said gate dielectric.

摘要翻译： 一种n阱电阻器件及其制造方法。 本发明的n阱电阻器件包括形成在n型硅区域中的第一n型区域和第二n型区域。 形成在所述n型硅区上的栅介质层。 形成在所述栅极电介质上的多晶硅栅极。

公开(公告)号：US06289447B1

公开(公告)日：2001-09-11

申请号：US09179492

申请日：1998-10-26

申请人： Alper Ilkbahar

发明人： Alper Ilkbahar

IPC分类号： G06F9445

CPC分类号： H03K17/164 ,  H03K19/0005 ,  H03K19/018585 ,  H03K19/1731

摘要： A method and apparatus for compensating system components based on system topology. The present invention provides a method and apparatus for performance optimization through topology dependent compensation. In one embodiment, one or more components of a computer system are coupled to a bus via self-compensated buffer(s). The self-compensated buffer(s) allow operating characteristics to be set via external signals such as voltage levels. System components have compensation units that receive external signals and configure the operating characteristics of the self-compensated buffer(s). In this manner a system designer may set operating characteristics for various system components based on the topology of the specific system rather than designing for a worst-case scenario.

摘要翻译： 一种基于系统拓扑补偿系统组件的方法和装置。 本发明提供一种通过拓扑依赖补偿进行性能优化的方法和装置。 在一个实施例中，计算机系统的一个或多个组件经由自补偿缓冲器耦合到总线。 自补偿缓冲器允许通过诸如电压电平的外部信号设置工作特性。 系统组件具有接收外部信号并配置自补偿缓冲器的工作特性的补偿单元。 以这种方式，系统设计者可以基于特定系统的拓扑而不是为最坏情况设计设计各种系统组件的操作特性。

公开(公告)号：US6016066A

公开(公告)日：2000-01-18

申请号：US45167

申请日：1998-03-19

申请人： Alper Ilkbahar

发明人： Alper Ilkbahar

IPC分类号： G11C7/10 ,  H03K5/1252 ,  H03K5/153 ,  H04L7/00 ,  H04L7/02 ,  H04L25/08 ,  H03K5/22

CPC分类号： G11C7/1084 ,  G11C7/1078 ,  H03K5/1252 ,  H03K5/153 ,  H04L25/085 ,  H04L7/0083 ,  H04L7/02

摘要： A method and apparatus for glitch protection for differential strobe input buffers in a source-synchronous environment. The present invention provides a solution to the problem of noise sensitivity of differential strobe input buffers in a source-synchronous environment, which may cause functional problems. The present invention enables the use of fully differential strobe signals to improve electrical performance of the source synchronous data transfers while removing the noise sensitivity problem associated with these signals. This is accomplished by providing a glitch protection circuit that provides protection against input glitches for a first predetermined period of time after each strobe transition. The present invention also provides a detection circuit that detects when both differential strobe signals are in the same logic state, which corresponds to a transition between bus masters (a dead cycle). The detection circuit causes the glitch protection circuit to latch the output signal of the glitch detection circuit.

公开(公告)号：US5898321A

公开(公告)日：1999-04-27

申请号：US824066

申请日：1997-03-24

申请人： Alper Ilkbahar ,  Bendik Kleveland

发明人： Alper Ilkbahar ,  Bendik Kleveland

IPC分类号： H03K17/16 ,  H03K19/0185

CPC分类号： H03K17/164

摘要： A method and an apparatus for adjusting the slew rate and impedance of a buffer in an integrated circuitry. In one embodiment, an integrated circuit buffer includes a pre-driver circuit, which includes a slew rate compensation circuit, coupled to a driver circuit, which includes an impedance compensation circuit. The slew rate compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground to provide a variable resistance to virtual rails for inverter circuits that are included in the pre-driver circuit. The slew rate compensation circuit is digitally controlled with slew rate control signals. The impedance compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground from an output node of the buffer. The parallel connected transistors of the impedance compensation circuit are digitally controlled with impedance control signals. The resistance to power and ground from the respective rails of the pre-driver circuit are controlled with the slew rate control signals to adjust the slew rate of data signals being driven by the buffer. The rails are shared among the inverters of the driver circuit to reduce the number of devices used by the buffer, thereby reducing the amount of circuit area and power used by the buffer.

摘要翻译： 一种用于调整集成电路中的缓冲器的转换速率和阻抗的方法和装置。 在一个实施例中，集成电路缓冲器包括预驱动器电路，其包括耦合到驱动器电路的压摆率补偿电路，该驱动器电路包括阻抗补偿电路。 转换速率补偿电路包括并联的p沟道晶体管，以将并联的n沟道晶体管接地，为包括在预驱动器电路中的反相器电路提供可变电阻。 转换速率补偿电路用压摆率控制信号进行数字控制。 阻抗补偿电路包括并联的p沟道晶体管，以将缓冲器的输出节点的N沟道晶体管并联连接到地。 阻抗补偿电路的并联晶体管通过阻抗控制信号进行数字控制。 通过转换速率控制信号控制来自预驱动器电路的相应导轨的电源和接地电阻，以调整由缓冲器驱动的数据信号的转换速率。 轨道在驱动器电路的反相器之间共享，以减少缓冲器使用的设备数量，从而减少缓冲器所使用的电路面积和功率。