公开(公告)号：US20050128805A1

公开(公告)日：2005-06-16

申请号：US11036961

申请日：2005-01-14

申请人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

公开(公告)号：US06381670B1

公开(公告)日：2002-04-30

申请号：US08823571

申请日：1997-03-25

申请人： Peter Wung Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Wen-Tan Fan

发明人： Peter Wung Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Wen-Tan Fan

IPC分类号： G06F1216

CPC分类号： G11C16/3418 ,  G11C8/10 ,  G11C8/12 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3431

摘要： A flash memory having over-erased cells eliminated and comprising adjustable erase and program conditions. The maximum and minimum threshold voltages of the cells are measured during the whole erase and program operations. The over-erased cells are shut down by applying a word line voltage lower than the minimum threshold voltage measured previously. Pre-program and repair operations for the over-erased cell are eliminated. Low read voltage is achieved. The erase and program conditions for the gate, source, drain voltage, width of a pulse, and number of pulses are adjustable in accordance with the threshold voltage to optimize the performance. A lookup table stores the relevant gate, source, drain voltage, width of a pulse, and number of pulses with respect to the threshold voltage for the adjustable conditions. The benefits achieved by the operation of the flash memory include high efficiency, long endurance, narrow threshold voltage distribution, low power consumption, and low process-sensitivity.

摘要翻译： 已经消除了擦除了单元的闪存，并且包括可调节的擦除和编程条件。 在整个擦除和编程操作期间测量单元的最大和最小阈值电压。 通过施加低于先前测量的最小阈值电压的字线电压来关闭过擦除的电池。 消除了被擦除的单元的预编程和修复操作。 实现了低读取电压。 栅极，源极，漏极电压，脉冲宽度和脉冲数的擦除和编程条件可根据阈值电压进行调节，以优化性能。 查找表存储相关的门，源，漏极电压，脉冲的宽度和相对于可调整条件的阈值电压的脉冲数。 闪存运行所带来的好处包括高效率，长寿命，窄阈值电压分配，低功耗，低工艺敏感性。

公开(公告)号：US5978277A

公开(公告)日：1999-11-02

申请号：US159793

申请日：1998-09-24

申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter Wung Lee

发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter Wung Lee

IPC分类号： G11C16/08 ,  G11C16/04

CPC分类号： G11C16/3409 ,  G11C16/08

摘要： New bias conditions for flash memory cells and X-decoder circuits for providing the bias conditions. In an erasing operation, a positive high voltage is provided to the bulk and a negative high voltage is provided to the control gate for establishing a sufficient electric field to induce electron tunneling effect. In an operation for repairing a cell's threshold voltage, the biased voltages are reversed. A first X-decoder circuit structure is presented for supplying positive and negative high voltages to the memory cells for block erasing or repairing. The first X-decoder circuit structure has a plurality of X-decoder blocks each being constructed in a separated X-decoder well, and the memory cells are fabricated in a separate common array well. A second X-decoder circuit structure is presented to provide an appropriate bias condition for erasing or repairing a small sector of word lines. For the second X-decoder circuit structure, each memory block is fabricated in a separated array well. Separated X-decoder wells are constructed to provide voltages to the word lines of memory blocks. Every word line in a memory block has an X-decoder driver so that the word line can be erased or repaired individually. A new layout is also presented for the construction of the X-decoder circuits.

摘要翻译： 闪存单元和X解码器电路的新偏置条件用于提供偏置条件。 在擦除操作中，向体积提供正高电压，并且向控制栅极提供负的高电压以建立足够的电场以诱发电子隧道效应。 在修复电池的阈值电压的操作中，偏置的电压被反转。 提出了第一个X解码器电路结构，用于向存储器单元提供正和负高电压用于块擦除或修复。 第一X解码器电路结构具有多个X解码器块，每个X解码器块分别构造在分离的X解码器阱中，并且存储单元制造在单独的公共阵列井中。 呈现第二X解码器电路结构以提供用于擦除或修复小扇区字线的适当偏置条件。 对于第二X解码器电路结构，每个存储器块以分离的阵列阱制造。 分离的X解码器阱被构造成向存储器块的字线提供电压。 存储块中的每个字线都有一个X解码器驱动程序，以便字线可以单独擦除或修复。 还介绍了X解码器电路结构的新布局。

公开(公告)号：US08775719B2

公开(公告)日：2014-07-08

申请号：US12807996

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/00

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1075 ,  G11C2216/22

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在并行接口上传输。 并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US20110072200A1

公开(公告)日：2011-03-24

申请号：US12807996

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/02 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1075 ,  G11C2216/22

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在并行接口上传输。 并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US08996785B2

公开(公告)日：2015-03-31

申请号：US12807997

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/00 ,  G11C16/32 ,  G11C16/04

CPC分类号： G11C16/32 ,  G11C16/0408

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US20110072201A1

公开(公告)日：2011-03-24

申请号：US12807997

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/02 ,  G11C16/06

CPC分类号： G11C16/32 ,  G11C16/0408

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US06687154B2

公开(公告)日：2004-02-03

申请号：US10364033

申请日：2003-02-11

申请人： Peter W. Lee ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Fu-Chang Hsu

IPC分类号： G11C1604

CPC分类号： H01L27/1126 ,  G11C11/005 ,  G11C16/0433 ,  G11C17/12 ,  H01L27/112 ,  H01L27/115

摘要： A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.

摘要翻译： 实现了存储单元装置。 存储单元器件包括具有栅极，漏极和源极的第一晶体管。 第二个晶体管具有栅极，漏极和源极。 第一晶体管漏极耦合到阵列位线。 第二晶体管源耦合到阵列源极线。 第一晶体管源耦合到第二晶体管漏极。 第一晶体管和第二晶体管包括一个闪存晶体管和一个掩模ROM晶体管。 可以读取掩模ROM晶体管的编程状态。

公开(公告)号：US20110051519A1

公开(公告)日：2011-03-03

申请号：US12807080

申请日：2010-08-27

申请人： Peter W. Lee ,  Kesheng Wang ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Kesheng Wang ,  Fu-Chang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/32 ,  G11C7/1075

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. An enable signal defines a beginning and termination of a reading or writing operation. Reading one nonvolatile memory array may be interrupted for another operation and then resumed.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 启用信号定义读取或写入操作的开始和结束。 读取一个非易失性存储器阵列可能被中断用于另一个操作，然后恢复。

公开(公告)号：US08355287B2

公开(公告)日：2013-01-15

申请号：US12806848

申请日：2010-08-23

申请人： Fu-Chang Hsu ,  Peter W. Lee

发明人： Fu-Chang Hsu ,  Peter W. Lee

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0458 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/10 ,  G11C16/16 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C16/3477 ,  G11C2211/5621

摘要： A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state.

摘要翻译： 用于NAND类型的双电荷保持晶体管NOR闪存单元的操作的方法和装置开始于擦除，验证将擦除的电荷保持晶体管的阈值电压电平擦除为已擦除的阈值电压电平。 然后，通过将NAND类双电荷保持晶体管NOR闪存单元的两个电荷保持晶体管中的一个编程为第一编程阈值电压电平，并编程NAND类似的双电荷保持的两个电荷保持晶体管中的另一个来进行方法 晶体管NOR闪存单元到第一编程阈值电压电平或第二编程阈值电压电平。 擦除阈值电压电平和第一和第二编程阈值电压电平的组合确定NAND类似的双电荷保持晶体管NOR闪存单元的内部数据状态，然后对其进行解码以确定外部数据逻辑状态。