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    Methods of fabricating non-volatile memory devices including a chlorine cured tunnel oxide layer
    92.
    发明授权
    Methods of fabricating non-volatile memory devices including a chlorine cured tunnel oxide layer 失效
    制造包括氯固化的隧道氧化物层的非易失性存储器件的方法

    公开(公告)号：US07799639B2

    公开(公告)日：2010-09-21

    申请号：US12123919

    申请日：2008-05-20

    申请人： Young-jin Noh ,  Si-Young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek

    发明人： Young-jin Noh ,  Si-Young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Fabrication of a nonvolatile memory device includes sequentially forming a tunnel oxide layer, a first conductive layer, and a nitride layer on a semiconductor substrate. A stacked pattern is formed from the tunnel oxide layer, the first conductive layer, and the nitride layer and a trench is formed in the semiconductor substrate adjacent to the stacked pattern. An oxidation process is performed to form a sidewall oxide layer on a sidewall of the trench and the first conductive layer. Chlorine is introduced into at least a portion of the stacked pattern subjected to the oxidation process. Introducing Cl into the stacked pattern may at least partially cure defects that are caused therein during fabrication of the structure.

    摘要翻译： 非易失性存储器件的制造包括在半导体衬底上依次形成隧道氧化物层，第一导电层和氮化物层。 从隧道氧化物层，第一导电层和氮化物层形成堆叠图案，并且在与堆叠图案相邻的半导体衬底中形成沟槽。 执行氧化处理以在沟槽和第一导电层的侧壁上形成侧壁氧化物层。 将氯气引入经历氧化过程的堆叠图案的至少一部分中。 将Cl引入堆叠图案可以至少部分地固化在结构制造期间在其中引起的缺陷。

    METHODS OF MANUFACTURING TRENCH ISOLATION STRUCTURES USING SELECTIVE PLASMA ION IMMERSION IMPLANTATION AND DEPOSITION (PIIID)
    93.
    发明申请
    METHODS OF MANUFACTURING TRENCH ISOLATION STRUCTURES USING SELECTIVE PLASMA ION IMMERSION IMPLANTATION AND DEPOSITION (PIIID) 有权
    使用选择性等离子体离子注入和沉积（PIIID）制造TRENCH隔离结构的方法

    公开(公告)号：US20090203189A1

    公开(公告)日：2009-08-13

    申请号：US12134760

    申请日：2008-06-06

    申请人： Dong-woon Shin ,  Tai-su Park ,  Si-Young Choi ,  Soo-Jin Hong ,  Mi-Jin Kim

    发明人： Dong-woon Shin ,  Tai-su Park ,  Si-Young Choi ,  Soo-Jin Hong ,  Mi-Jin Kim

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823456 ,  H01L27/0921 ,  H01L27/105

    摘要： A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.

    摘要翻译： 通过在衬底中形成沟槽并且在衬底中的沟槽的子集上选择性地执行等离子体离子注入植入和沉积（PIIID）来制造半导体器件。 PIIID可以仅在衬底中的至少一个沟槽的表面的一部分上进行。 半导体器件可以包括其中具有第一，第二和第三沟槽的半导体衬底以及不对第一沟槽进行线条化的氧化物衬层，其不线性化第二沟槽并且部分地对第三沟槽进行排列。

    Non-volatile memory device and methods of forming the same
    95.
    发明申请
    Non-volatile memory device and methods of forming the same 有权
    非易失性存储器件及其形成方法

    公开(公告)号：US20090045448A1

    公开(公告)日：2009-02-19

    申请号：US12222568

    申请日：2008-08-12

    申请人： Seung-Jae Baik ,  Si-Young Choi ,  Ki-Hyun Hwang

    发明人： Seung-Jae Baik ,  Si-Young Choi ,  Ki-Hyun Hwang

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/42352

    摘要： Example embodiments provide a non-volatile memory device and methods of forming the same. The non-volatile memory device may define an active region in a semiconductor substrate, and may include a device isolation layer extending in a first direction, bit lines in the semiconductor substrate, the bit lines extending in a second direction which intersects the first direction; word lines extending in the first direction and covering the active region; and charge storage patterns between the word lines and active region, wherein the charge storage patterns may be in pairs on both edges of the bit lines, and a pair of charge storage patterns may be spaced apart from each other by the word lines.

    摘要翻译： 示例性实施例提供非易失性存储器件及其形成方法。 非易失性存储器件可以在半导体衬底中限定有源区，并且可以包括沿第一方向延伸的器件隔离层，半导体衬底中的位线，沿与第一方向相交的第二方向延伸的位线; 字线在第一方向上延伸并覆盖有源区; 并且对字线和有源区域之间的存储模式进行充电，其中电荷存储模式可以在位线的两个边缘上成对配对，并且一对电荷存储模式可以通过字线彼此间隔开。

    Semiconductor device and method of manufacturing the same
    96.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20080308876A1

    公开(公告)日：2008-12-18

    申请号：US12155969

    申请日：2008-06-12

    申请人： Hye-Lan Lee ,  Si-Young Choi ,  Sang-Bom Kang ,  Si-Hyung Lee ,  Sang-Jin Hyun

    发明人： Hye-Lan Lee ,  Si-Young Choi ,  Sang-Bom Kang ,  Si-Hyung Lee ,  Sang-Jin Hyun

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L29/4958 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/4966

    摘要： A semiconductor device includes a first gate structure on a first region of a substrate, the first gate structure including sequentially formed a first insulating layer pattern, a first conductive layer pattern, and a first polysilicon layer pattern doped with first impurities of a first conductivity type, a first source/drain in the first region of the substrate doped with second impurities of a second conductivity type, a second gate structure on a second region of the substrate, the second gate structure including sequentially formed a second insulating layer pattern, a second conductive layer pattern, and a second polysilicon layer pattern doped with third impurities with the first conductivity type, and a second source/drain in the second region of the substrate doped with fourth impurities having a conductivity type opposite the second conductivity.

    摘要翻译： 半导体器件包括在衬底的第一区域上的第一栅极结构，第一栅极结构包括顺序地形成第一绝缘层图案，第一导电层图案和掺杂有第一导电类型的第一杂质的第一多晶硅层图案 掺杂有第二导电类型的第二杂质的衬底的第一区域中的第一源极/漏极，在衬底的第二区域上的第二栅极结构，第二栅极结构依次形成第二绝缘层图案，第二栅极结构 导电层图案和掺杂有第一导电类型的第三杂质的第二多晶硅层图案，以及掺杂有具有与第二导电性相反的导电类型的第四杂质的第二基底的第二源极/漏极。

    Fin field effect transistors having multi-layer fin patterns
    97.
    发明授权
    Fin field effect transistors having multi-layer fin patterns 失效
    鳍场效应晶体管具有多层翅片图案

    公开(公告)号：US07323710B2

    公开(公告)日：2008-01-29

    申请号：US10870743

    申请日：2004-06-17

    申请人： Young-Pil Kim ,  Sun-Ghil Lee ,  Si-Young Choi

    发明人： Young-Pil Kim ,  Sun-Ghil Lee ,  Si-Young Choi

    IPC分类号： H01L29/06 ,  H01L31/00

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

    摘要： A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least one direction. In addition, the first and second semiconductor patterns may be alternately stacked to increase the height of the fin pattern, such that one of the first and second patterns can reduce stress from the other of the first and second patterns. The first and second semiconductor patterns may be formed of strained silicon and silicon-germanium, where the silicon-germanium patterns can reduce stress from the strained silicon patterns. Therefore, both the number of carriers and the mobility of carriers in the transistor channel may be increased, improving performance of the fin field effect transistor. Related methods are also discussed.

    摘要翻译： 鳍状场效应晶体管具有从半导体衬底突出的鳍状图案。 鳍状图案包括堆叠的第一半导体图案和第二半导体图案。 第一和第二半导体图案具有在至少一个方向上大于衬底的晶格宽度的晶格宽度。 此外，第一和第二半导体图案可以交替堆叠以增加鳍片图案的高度，使得第一和第二图案中的一个可以减小来自第一和第二图案中的另一个的应力。 第一和第二半导体图案可以由应变硅和硅 - 锗形成，其中硅 - 锗图案可以减小应变硅图案的应力。 因此，可以增加晶体管沟道中的载流子数和载流子的迁移率，从而提高鳍式场效应晶体管的性能。 还讨论了相关方法。

    Vertical channel field effect transistors having insulating layers thereon and methods of fabricating the same
    98.
    发明申请
    Vertical channel field effect transistors having insulating layers thereon and methods of fabricating the same 有权
    具有绝缘层的垂直沟道场效应晶体管及其制造方法

    公开(公告)号：US20050145932A1

    公开(公告)日：2005-07-07

    申请号：US10780067

    申请日：2004-02-17

    申请人： Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    发明人： Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L29/10

    CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

    摘要： A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.

    摘要翻译： 场效应晶体管可以包括从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，以及在垂直沟道的侧壁上朝衬底延伸超过源/漏极的绝缘层 区域交界处 晶体管还可以包括在离开衬底的侧壁上延伸超过绝缘层的氮化物层，在侧壁上延伸的第二绝缘层，其通过氮化物层与沟道分离，以及栅电极 侧壁朝向衬底以超出源/漏区结。 还公开了相关方法。