公开(公告)号：US20090203189A1

公开(公告)日：2009-08-13

申请号：US12134760

申请日：2008-06-06

申请人： Dong-woon Shin ,  Tai-su Park ,  Si-Young Choi ,  Soo-Jin Hong ,  Mi-Jin Kim

发明人： Dong-woon Shin ,  Tai-su Park ,  Si-Young Choi ,  Soo-Jin Hong ,  Mi-Jin Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823456 ,  H01L27/0921 ,  H01L27/105

摘要： A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.

摘要翻译： 通过在衬底中形成沟槽并且在衬底中的沟槽的子集上选择性地执行等离子体离子注入植入和沉积（PIIID）来制造半导体器件。 PIIID可以仅在衬底中的至少一个沟槽的表面的一部分上进行。 半导体器件可以包括其中具有第一，第二和第三沟槽的半导体衬底以及不对第一沟槽进行线条化的氧化物衬层，其不线性化第二沟槽并且部分地对第三沟槽进行排列。

公开(公告)号：US20100055856A1

公开(公告)日：2010-03-04

申请号：US12461896

申请日：2009-08-27

申请人： Soo-Jin Hong ,  Jong-Ryeol Yoo ,  Dong-Woon Shin ,  Si-Young Choi ,  Sun-Ghil Lee

发明人： Soo-Jin Hong ,  Jong-Ryeol Yoo ,  Dong-Woon Shin ,  Si-Young Choi ,  Sun-Ghil Lee

IPC分类号： H01L21/8242 ,  H01L21/31

CPC分类号： H01L21/02236 ,  H01L21/022 ,  H01L21/31155 ,  H01L21/31641 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897

摘要： A method of forming an oxide layer on a trench, a method of forming a semiconductor device, and a semiconductor device, the method of forming an oxide layer on a trench including forming a first trench in a first portion of a substrate and a second trench in a second portion of the substrate, the first portion being different from the second portion, performing a plasma doping process on at least one of the first portion and the second portion to implant an impurity therein, and performing an oxidation process to form an oxide layer on the substrate, a thickness of the oxide layer being determined by the impurity implanted in the substrate.

摘要翻译： 在沟槽上形成氧化物层的方法，形成半导体器件的方法和半导体器件，在沟槽上形成氧化物层的方法，包括在衬底的第一部分中形成第一沟槽和第二沟槽 在所述衬底的第二部分中，所述第一部分与所述第二部分不同，在所述第一部分和所述第二部分中的至少一个上执行等离子体掺杂工艺以在其中注入杂质，并进行氧化处理以形成氧化物 层，该氧化物层的厚度由注入衬底中的杂质决定。

公开(公告)号：US07514744B2

公开(公告)日：2009-04-07

申请号：US11322335

申请日：2005-12-30

申请人： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

发明人： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.

摘要翻译： 半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。 该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。 与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。 表面绝缘层与源极/漏极区之间的界面包括多个界面状态。 紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。 载体积聚层沿着间隔物下的界面延伸。 还讨论了相关方法。

公开(公告)号：US06740955B1

公开(公告)日：2004-05-25

申请号：US10431606

申请日：2003-05-08

申请人： Soo-Jin Hong ,  Jin-Hwa Heo

发明人： Soo-Jin Hong ,  Jin-Hwa Heo

IPC分类号： H01L2900

CPC分类号： H01L21/76224

摘要： A method of forming a trench device isolation structure, wherein, after forming a trench in a predetermined area of a semiconductor substrate, a lower isolation pattern, an upper liner pattern, and an upper isolation pattern are sequentially formed to fill the trench. A lower device isolation layer is formed on an entire surface of the semiconductor substrate, and then etched to form the lower isolation pattern so that a top surface of the lower isolation pattern is lower than a top surface of the semiconductor substrate. An upper liner layer and an upper device isolation layer are formed on the entire surface of the semiconductor substrate including the lower isolation pattern, and then etched to form the upper liner pattern. As a result, the upper liner pattern covers the top surface of the lower isolation pattern and surrounds the bottom and the sidewall of the upper isolation pattern.

摘要翻译： 一种形成沟槽器件隔离结构的方法，其中，在半导体衬底的预定区域中形成沟槽之后，依次形成下隔离图案，上衬垫图案和上隔离图案以填充沟槽。 在半导体衬底的整个表面上形成下部器件隔离层，然后蚀刻以形成下部隔离图案，使得下部隔离图案的顶表面低于半导体衬底的顶表面。 在包括下隔离图案的半导体衬底的整个表面上形成上衬层和上器件隔离层，然后蚀刻以形成上衬垫图案。 结果，上衬垫图案覆盖下隔离图案的顶表面并且围绕上隔离图案的底部和侧壁。

公开(公告)号：US06251746B1

公开(公告)日：2001-06-26

申请号：US09415475

申请日：1999-10-08

申请人： Soo-Jin Hong ,  Yung-Seob Yu ,  Bon-Young Koo ,  Byung-Ki Kim ,  Seung-Mok Shin

发明人： Soo-Jin Hong ,  Yung-Seob Yu ,  Bon-Young Koo ,  Byung-Ki Kim ,  Seung-Mok Shin

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： Methods of forming trench isolation regions include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a trench in the semiconductor substrate, using the trench masking layer as etching mask. A trench nitride layer comprising a second material different from the first material is then formed on a sidewall of the trench and on a sidewall of the trench masking layer. The trench is then filled with a trench insulating material (e.g., USG). The trench masking layer is then removed by selectively etching the trench masking layer with an etchant that selectively etches the first material at a higher rate than the second material. This step of removing the trench masking layer results in exposure of a protruding portion of the trench nitride layer but does not cause the trench nitride layer to become recessed. The trench insulating material and the trench nitride layer are then etched back to define the trench isolation region.

摘要翻译： 形成沟槽隔离区的方法包括以下步骤：使用沟槽掩模层作为蚀刻掩模，在半导体衬底上形成包含第一材料（例如多晶硅）的沟槽屏蔽层，然后蚀刻半导体衬底中的沟槽。 然后在沟槽的侧壁和沟槽掩模层的侧壁上形成包括不同于第一材料的第二材料的沟槽氮化物层。 然后用沟槽绝缘材料（例如USG）填充沟槽。 然后通过用比第二材料更高的速率选择性地蚀刻第一材料的蚀刻剂选择性蚀刻沟槽掩模层来去除沟槽掩模层。 去除沟槽屏蔽层的这个步骤导致了沟槽氮化物层的突出部分的曝光，但是不会使沟槽氮化物层变凹陷。 然后将沟槽绝缘材料和沟槽氮化物层回蚀刻以限定沟槽隔离区域。

公开(公告)号：US06756654B2

公开(公告)日：2004-06-29

申请号：US10215342

申请日：2002-08-09

申请人： Jin-Hwa Heo ,  Soo-Jin Hong

发明人： Jin-Hwa Heo ,  Soo-Jin Hong

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.

摘要翻译： 本发明涉及一种结构和方法，通过该结构和方法可以实现在衬底的第一和第二区域中形成的宽沟槽和窄沟槽的沟槽隔离，而不会在隔离层中形成空隙，露出隔离层 ，或在后续过程中门之间的电桥。 在第一和第二沟槽中的衬底上形成下隔离层。 图案化下部隔离层以填充第一沟槽的下部区域，并且形成上部隔离图案以填充第二沟槽和第一沟槽的其余部分。 第一沟槽的纵横比减小，从而防止在上隔离层中发生空隙或上隔离层与基板之间的间隙。

公开(公告)号：US06699799B2

公开(公告)日：2004-03-02

申请号：US10134747

申请日：2002-04-30

申请人： Dong-Ho Ahn ,  Soo-Jin Hong ,  Jung-Il Lee ,  Kyung-won Park

发明人： Dong-Ho Ahn ,  Soo-Jin Hong ,  Jung-Il Lee ,  Kyung-won Park

IPC分类号： H01L21469

CPC分类号： H01L21/0234 ,  H01L21/02134 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/31053 ,  H01L21/316 ,  H01L21/76229

摘要： A method of forming a semiconductor device includes a liner is conformally stacked on a semiconductor substrate before coating an SOG layer thereon, and then curing the SOG layer, preferably in an ambient of oxygen radicals formed at a temperature of 1000° C. or higher when oxygen and hydrogen are supplied. The oxygen radicals are preferably formed by irradiating ultraviolet rays to ozone or forming oxygen plasma. The SOG layer is preferably made of a polysilazane-based material that may promote a conversion of the SOG layer into a silicon oxide layer.

摘要翻译： 一种形成半导体器件的方法包括：在涂覆SOG层之前，在半导体衬底上保形地层叠衬垫，然后固化SOG层，优选在1000℃或更高温度下形成的氧自由基的环境中固化 供应氧气和氢气。 氧自由基优选通过将紫外线照射到臭氧或形成氧等离子体来形成。 SOG层优选由可以促进SOG层转化为氧化硅层的基于聚硅氮烷的材料制成。

公开(公告)号：US06583025B2

公开(公告)日：2003-06-24

申请号：US09847280

申请日：2001-05-03

申请人： Soo-Jin Hong

发明人： Soo-Jin Hong

IPC分类号： H01L212176

CPC分类号： H01L21/76224

摘要： A method of forming a trench isolation structure prevents a nitride liner from being over-etched, i.e., prevents the so-called dent phenomenon from occurring. An etching mask pattern is formed on a semiconductor substrate. A trench is formed in the substrate by using the etching mask pattern as an etching mask. A nitride liner, serving as an oxidation barrier layer, is formed at the sides and bottom of the trench, and is then annealed in a furnace to density the same. In a subsequent etching process, such as that used to remove the etching mask pattern, the densified nitride liner resists being etched. Accordingly, a trench isolation structure having a good profile is produced.

公开(公告)号：US08319260B2

公开(公告)日：2012-11-27

申请号：US12805400

申请日：2010-07-29

申请人： Deok-Hyung Lee ,  Soo-Jin Hong ,  Seong-Hoon Jeong

发明人： Deok-Hyung Lee ,  Soo-Jin Hong ,  Seong-Hoon Jeong

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/7845

摘要： In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.

摘要翻译： 在半导体器件中，形成半导体器件的方法包括具有第一栅极氧化层图案的第一栅极结构，包含比硅大的原子的第一多晶硅层图案和在拉伸应力下的基板上的第一硬掩模层图案。 在第一栅极结构的两侧的衬底的表面下方形成N型杂质区。 具有第二栅极氧化物层图案的第二栅极结构，在压缩应力下在基底上含有小于硅的原子的第二多晶硅层图案和第二硬掩模层图案。 此外，在第二栅极结构的两侧在基板的表面下方形成P型杂质区。 半导体器件具有良好的器件特性。

公开(公告)号：US20060145254A1

公开(公告)日：2006-07-06

申请号：US11322335

申请日：2005-12-30

申请人： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

发明人： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

IPC分类号： H01L29/76

CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.

摘要翻译： 半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。 该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。 与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。 表面绝缘层与源极/漏极区之间的界面包括多个界面状态。 紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。 载体积聚层沿着间隔物下的界面延伸。 还讨论了相关方法。