公开(公告)号：US09385201B2

公开(公告)日：2016-07-05

申请号：US14297822

申请日：2014-06-06

Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L21/84 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

公开(公告)号：US20160190314A1

公开(公告)日：2016-06-30

申请号：US14588318

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Chun-chen Yeh ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7855 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28141 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7831 ,  H01L29/785

Abstract: A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.

Abstract translation: 垂直狭缝晶体管包括半导体衬底中的凸起的源极，漏极和沟道区。 两个栅极位于半导体衬底的相应侧壁附近。 电介质材料将栅电极与源区和漏区分开。

公开(公告)号：US20160111513A1

公开(公告)日：2016-04-21

申请号：US14984688

申请日：2015-12-30

Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L29/165 ,  H01L29/06 ,  H01L29/16 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract translation: 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是当金属用于形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分发生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。

公开(公告)号：US09318579B2

公开(公告)日：2016-04-19

申请号：US14300506

申请日：2014-06-10

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片，以及覆盖半导体鳍片的栅极。 门具有锥形外表面。 在栅极附近形成第一对侧壁间隔物，露出的锥形外表面也被限定。 在露出的锥形外表面上去除栅极的部分以限定凹部。 形成第二对侧壁间隔件，覆盖第一对侧壁间隔件和凹部。 源极/漏极区域形成在半导体鳍片上。

公开(公告)号：US09281382B2

公开(公告)日：2016-03-08

申请号：US14295618

申请日：2014-06-04

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/785

Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

Abstract translation: 制造半导体器件的方法可以包括在衬底之上形成多个横向间隔开的半导体鳍片，以及在横向间隔开的半导体鳍片之间形成第一电介质材料的区域。 该方法还可以包括：从多个半导体鳍片中选择性地移除至少一个中间半导体鳍片，以限定第一介电材料的相应区域之间的至少一个沟槽，以及形成与第一电介质不同的第二电介质材料的区域 所述至少一个沟槽用于在相邻的半导体鳍片之间提供至少一个隔离柱。

公开(公告)号：US09269712B2

公开(公告)日：2016-02-23

申请号：US14068340

申请日：2013-10-31

Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Hyun-Jin Cho

IPC: H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.

Abstract translation: 制造半导体器件的方法可以包括在包括第一半导体材料的衬底上形成第一半导体层，在包括第二半导体材料的第一半导体层上形成第二半导体层，以及在第二半导体层上形成掩模区域和蚀刻 通过第一和第二半导体层在衬底上限定多个间隔开的柱。 该方法可以进一步包括在横向围绕柱和掩模区域形成氧化物层，以及去除掩模区域并在横向相邻的每个柱顶上相应的氧化物层部分上形成内部间隔物。 该方法还可以包括通过相应的内部间隔物之间​​的第二半导体层进行蚀刻，以从每个支柱形成第二半导体材料的一对半导体鳍片，以及去除内部间隔物并在每个半导体鳍片之下形成氧化物。

公开(公告)号：US20150372104A1

公开(公告)日：2015-12-24

申请号：US14312418

申请日：2014-06-23

Applicant: STMICROELCTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/51 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/10 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract translation: 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是，当使用金属来形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分可以产生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。

公开(公告)号：US20190259673A1

公开(公告)日：2019-08-22

申请号：US16399808

申请日：2019-04-30

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/161 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L21/266 ,  H01L27/12 ,  H01L27/02 ,  H01L21/308 ,  H01L21/265

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US10319647B2

公开(公告)日：2019-06-11

申请号：US15890001

申请日：2018-02-06

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/161 ,  H01L29/423

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US10256351B2

公开(公告)日：2019-04-09

申请号：US15723149

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/00 ,  H01L29/788 ,  H01L21/02

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.