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    Semiconductor device providing enhanced fin isolation and related methods
    1.
    发明授权
    Semiconductor device providing enhanced fin isolation and related methods 有权
    提供增强散热片隔离和相关方法的半导体器件

    公开(公告)号：US09269712B2

    公开(公告)日：2016-02-23

    申请号：US14068340

    申请日：2013-10-31

    Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

    Inventor： Qing Liu ,  Ruilong Xie ,  Hyun-Jin Cho

    IPC: H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/06

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.

    Abstract translation: 制造半导体器件的方法可以包括在包括第一半导体材料的衬底上形成第一半导体层，在包括第二半导体材料的第一半导体层上形成第二半导体层，以及在第二半导体层上形成掩模区域和蚀刻 通过第一和第二半导体层在衬底上限定多个间隔开的柱。 该方法可以进一步包括在横向围绕柱和掩模区域形成氧化物层，以及去除掩模区域并在横向相邻的每个柱顶上相应的氧化物层部分上形成内部间隔物。 该方法还可以包括通过相应的内部间隔物之间​​的第二半导体层进行蚀刻，以从每个支柱形成第二半导体材料的一对半导体鳍片，以及去除内部间隔物并在每个半导体鳍片之下形成氧化物。

    SEMICONDUCTOR DEVICE PROVIDING ENHANCED FIN ISOLATION AND RELATED METHODS
    2.
    发明申请
    SEMICONDUCTOR DEVICE PROVIDING ENHANCED FIN ISOLATION AND RELATED METHODS 有权
    提供加强熔融隔离的半导体器件及相关方法

    公开(公告)号：US20150115370A1

    公开(公告)日：2015-04-30

    申请号：US14068340

    申请日：2013-10-31

    Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

    Inventor： Qing LIU ,  Ruilong Xie ,  Hyun-Jin Cho

    IPC: H01L27/088 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8234

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.

    Abstract translation: 制造半导体器件的方法可以包括在包括第一半导体材料的衬底上形成第一半导体层，在包括第二半导体材料的第一半导体层上形成第二半导体层，以及在第二半导体层上形成掩模区域和蚀刻 通过第一和第二半导体层在衬底上限定多个间隔开的柱。 该方法可以进一步包括在横向围绕柱和掩模区域形成氧化物层，以及去除掩模区域并在横向相邻的每个柱顶上相应的氧化物层部分上形成内部间隔物。 该方法还可以包括通过相应的内部间隔物之间​​的第二半导体层进行蚀刻，以从每个支柱形成第二半导体材料的一对半导体鳍片，以及去除内部间隔物并在每个半导体鳍片之下形成氧化物。

    Topological method to build self-aligned MTJ without a mask
    6.
    发明授权
    Topological method to build self-aligned MTJ without a mask 有权
    构建自对准MTJ无掩模的拓扑方法

    公开(公告)号：US09190260B1

    公开(公告)日：2015-11-17

    申请号：US14540504

    申请日：2014-11-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Seowoo Nam ,  Hyun-Jin Cho

    IPC: H01L43/12 ,  H01L21/02 ,  H01L27/22

    CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

    Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

    Abstract translation: 提供了不使用光刻掩模形成自对准MTJ的方法和所得到的器件。 实施例包括在金属层上形成第一电极，金属层凹入低k电介质层中; 在第一电极上形成MTJ层; 在MTJ层上形成第二电极; 将所述第二电极，所述MTJ层和所述第一电极的部分去除到所述低k电介质层; 在所述第二电极和所述低k电介质层上形成氮化硅基层; 并将氮化硅基层平坦化到第二电极。

    Magnetic tunnel junction between metal layers of a semiconductor device
    8.
    发明授权
    Magnetic tunnel junction between metal layers of a semiconductor device 有权
    半导体器件的金属层之间的磁隧道结

    公开(公告)号：US09236557B2

    公开(公告)日：2016-01-12

    申请号：US14156210

    申请日：2014-01-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Hyun-Jin Cho

    IPC: H01L21/00 ,  H01L43/02 ,  H01L43/12

    CPC classification number: H01L43/02 ,  H01L43/12

    Abstract: Embodiments herein provide a magnetic tunnel junction (MTJ) formed between metal layers of a semiconductor device. Specifically, provided is an approach for forming the semiconductor device using only one or two masks, the approach comprising: forming a first metal layer in a dielectric layer of the semiconductor device, forming a bottom electrode layer over the first metal layer, forming a MTJ over the bottom electrode layer, forming a top electrode layer over the MTJ, patterning the top electrode layer and the MTJ with a first mask, and forming a second metal layer over the top electrode layer. Optionally, the bottom electrode layer may be patterned using a second mask. Furthermore, in another embodiment, an insulator layer (e.g., manganese) is formed atop the dielectric layer, wherein a top surface of the first metal layer remains exposed following formation of the insulator layer such that the bottom electrode layer contacts the top surface of the first metal layer. By forming the MTJ between the metal layers using only one or two masks, the overall number of processing steps is reduced.

    Abstract translation: 本文的实施例提供了形成在半导体器件的金属层之间的磁性隧道结（MTJ）。 具体地，提供了仅使用一个或两个掩模形成半导体器件的方法，所述方法包括：在所述半导体器件的电介质层中形成第一金属层，在所述第一金属层上形成底部电极层，形成MTJ 在所述底部电极层上方，在所述MTJ上形成顶部电极层，用第一掩模图案化所述顶部电极层和所述MTJ，以及在所述顶部电极层上方形成第二金属层。 可选地，可以使用第二掩模对底部电极层进行图案化。 此外，在另一个实施例中，绝缘体层（例如，锰）形成在电介质层的顶部，其中第一金属层的顶表面在形成绝缘体层之后保持暴露，使得底部电极层接触绝缘层的顶表面 第一金属层。 通过仅使用一个或两个掩模在金属层之间形成MTJ，减少了处理步骤的总数。

    MAGNETIC TUNNEL JUNCTION BETWEEN METAL LAYERS OF A SEMICONDUCTOR DEVICE
    9.
    发明申请
    MAGNETIC TUNNEL JUNCTION BETWEEN METAL LAYERS OF A SEMICONDUCTOR DEVICE 有权
    半导体器件金属层之间的磁性隧道结

    公开(公告)号：US20150200353A1

    公开(公告)日：2015-07-16

    申请号：US14156210

    申请日：2014-01-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Hyun-Jin Cho

    IPC: H01L43/02 ,  H01L43/12

    CPC classification number: H01L43/02 ,  H01L43/12

    Abstract: Embodiments herein provide a magnetic tunnel junction (MTJ) formed between metal layers of a semiconductor device. Specifically, provided is an approach for forming the semiconductor device using only one or two masks, the approach comprising: forming a first metal layer in a dielectric layer of the semiconductor device, forming a bottom electrode layer over the first metal layer, forming a MTJ over the bottom electrode layer, forming a top electrode layer over the MTJ, patterning the top electrode layer and the MTJ with a first mask, and forming a second metal layer over the top electrode layer. Optionally, the bottom electrode layer may be patterned using a second mask. Furthermore, in another embodiment, an insulator layer (e.g., manganese) is formed atop the dielectric layer, wherein a top surface of the first metal layer remains exposed following formation of the insulator layer such that the bottom electrode layer contacts the top surface of the first metal layer. By forming the MJT between the metal layers using only one or two masks, the overall number of processing steps is reduced.

    Abstract translation: 本文的实施例提供了形成在半导体器件的金属层之间的磁性隧道结（MTJ）。 具体地，提供了仅使用一个或两个掩模形成半导体器件的方法，所述方法包括：在所述半导体器件的电介质层中形成第一金属层，在所述第一金属层上形成底电极层，形成MTJ 在所述底部电极层上方，在所述MTJ上形成顶部电极层，用第一掩模图案化所述顶部电极层和所述MTJ，以及在所述顶部电极层上方形成第二金属层。 可选地，可以使用第二掩模对底部电极层进行图案化。 此外，在另一个实施例中，绝缘体层（例如，锰）形成在电介质层的顶部，其中第一金属层的顶表面在形成绝缘体层之后保持暴露，使得底部电极层接触绝缘层的顶表面 第一金属层。 通过仅使用一个或两个掩模在金属层之间形成MJT，减少了处理步骤的总数。

    CONFORMAL DOPING FOR FINFET DEVICES
    10.
    发明申请
    CONFORMAL DOPING FOR FINFET DEVICES 有权
    FINFET器件的一致性掺杂

    公开(公告)号：US20150079773A1

    公开(公告)日：2015-03-19

    申请号：US14028517

    申请日：2013-09-16

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Veeraraghavan S. Basker ,  Nathaniel Berliner ,  Hyun-Jin Cho ,  Johnathan Faltermeler ,  Kam-Leung Lee ,  Tenko Yamashita

    IPC: H01L21/18

    CPC classification number: H01L21/18 ,  H01L21/2236 ,  H01L21/2251 ,  H01L21/845 ,  H01L29/66803

    Abstract: A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFETfins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.

    Abstract translation: 在包括NFET鳍片和PFET鳍片的半导体衬底上的FinFET器件的共形掺杂工艺。 在第一示例性实施例中，N型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。 将半导体衬底退火以将N型掺杂剂从N型掺杂剂组合物驱动到NFET鳍中。 P型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。 将半导体衬底退火以将P型掺杂剂从P型掺杂剂组合物驱动到PFET鳍中。 在第二示例性实施例中，可以用第一掺杂剂组合物覆盖NFET烯烃和PFET鳍中的一个，然后第二掺杂剂组合物可以覆盖NFET鳍和PFET鳍，然后进行退火以在两种掺杂剂中驱动。

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