公开(公告)号：US20190295669A1

公开(公告)日：2019-09-26

申请号：US15928976

申请日：2018-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Piyush Dak ,  Wei Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Mohan Dunga

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programing operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

公开(公告)号：US10381083B1

公开(公告)日：2019-08-13

申请号：US16018018

申请日：2018-06-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kun-Huan Shih ,  Matthias Baenninger ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11524

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel potential gradient near the select gate transistors is reduced when the voltages of the bit line and the substrate are suitably controlled. In one approach, the voltage of the substrate at a source end of the memory string is increased to an intermediate level first before being increased to the erase voltage threshold level while the voltage of the bit line is held at a reference voltage level to delay floating the voltage of the bit line. Another approach builds off the first approach by temporarily decreasing the voltage of the bit line to a negative level before letting the voltage of the bit line to float at the same time as the voltage of the substrate is increased to the erase voltage threshold level.

公开(公告)号：US12112812B2

公开(公告)日：2024-10-08

申请号：US17884929

申请日：2022-08-10

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Dengtao Zhao ,  Xiang Yang

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10

Abstract: Non-volatile memory cells are programmed by pre-charging channels of unselected non-volatile memory cells connected to a selected data word line, boosting the channels of unselected non-volatile memory cells connected to the selected data word line after the pre-charging and applying a program voltage pulse to selected non-volatile memory cells connected to the selected data word line while boosting. The pre-charging includes applying pre-charge voltages to one set of data word lines and dummy word line(s) as well as applying overdrive voltages to another set of data word lines connected to already programmed memory cells. At the end of the pre-charging, the dummy word lines are ramped down to a resting voltage prior to lowering the data word lines to one or more resting voltages.

公开(公告)号：US20240274200A1

公开(公告)日：2024-08-15

申请号：US18225375

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Xiang Yang

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/30

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/30

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the word lines and the strings and is configured to successively apply one of a series of pulses of a program voltage to each selected one of the word lines to program the memory cells connected thereto during a program operation. The control means is also configured to utilize a time of a preliminary period of the program operation based on the one of the series of pulses of the program voltage being applied. The preliminary period of the program operation is before the series of pulses of the program voltage are applied to each selected one of the plurality of word lines.

公开(公告)号：US12057166B2

公开(公告)日：2024-08-06

申请号：US17487347

申请日：2021-09-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/08 ,  G11C16/16 ,  H10B41/40 ,  H10B43/40

CPC classification number: G11C16/08 ,  G11C16/16 ,  H10B41/40 ,  H10B43/40

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. The memory cells are configured to retain a threshold voltage corresponding to memory states. Each one of the strings has drain-side select gate transistors on a drain-side of the one of the strings including top drain-side select gate transistors connected to bit lines and coupled to the memory cells of the-one of the strings. A control means is coupled to the word lines and bit lines and is configured to apply an unselected top voltage to unselected ones of the top drain-side select gate transistors during a memory operation. The control means is also configured to simultaneously apply a selected top voltage to selected ones top drain-side select gate transistors during the memory operation. The unselected top voltage is intentionally different electrically than the selected top voltage.

公开(公告)号：US20240203506A1

公开(公告)日：2024-06-20

申请号：US18357399

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C5/06 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C5/063 ,  G11C16/3404

Abstract: A non-volatile memory system programs memory cells from an erased threshold voltage distribution to programmed threshold voltage distributions by performing hole pre-charging of channels of unselected NAND strings in a selected block of a selected plane including applying a source voltage to a selected signal line of a plurality of signal lines that are isolated from each other. The selected signal line is positioned between the selected block and an unselected block and is connected to a selected source line of a plurality of source lines that are isolated from each other. The selected source line is connected to the selected block. The source voltage is greater in magnitude than any predetermined threshold voltage of the erased threshold voltage distribution. After the pre-charging, the system boosts channels of unselected NAND strings in the selected block and applies a program voltage to selected NAND strings in the selected block.

公开(公告)号：US11972806B2

公开(公告)日：2024-04-30

申请号：US17837744

申请日：2022-06-10

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08

Abstract: The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided and is configured to read the memory cells of a selected word line. The control circuitry separates the memory cells of the selected word line into a first group of memory cells, which are located on a side of the word line are near a voltage driver, and a second group of memory cells, which are located on an opposite side of the word line from the voltage driver. The control circuitry reads the memory cells of the first group using a first read mode and reads the memory cells of the second group using a second read mode that is different than the first read mode to reduce a fail bit count during read.

公开(公告)号：US11961573B2

公开(公告)日：2024-04-16

申请号：US17533292

申请日：2021-11-23

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang ,  Dengtao Zhao

IPC: G11C16/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A plurality of memory programming the memory cells to at least one programmed data state in a plurality of program-verify iterations. In each iteration, after a programming pulse, a sensing operation is conducted to compare the threshold voltages of the memory cells to a low verify voltage associated with a first programmed data state and to a high very voltage associated with the first programmed data state. The sensing operation includes discharging a sense node through a bit line coupled to one of the memory cells and monitoring a discharge time of the sense node. At least one aspect of the sensing operation is temperature dependent so that a voltage gap between the high and low verify voltages is generally constant across a range of temperatures.

公开(公告)号：US11942157B2

公开(公告)日：2024-03-26

申请号：US17697252

申请日：2022-03-17

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Xiaochen Zhu

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/0483 ,  H10B43/27

Abstract: An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line.

公开(公告)号：US20240078028A1

公开(公告)日：2024-03-07

申请号：US17901310

申请日：2022-09-01

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Xiang Yang

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Technology is disclosed herein for managing timing parameters when programming memory cells. Timing parameters used sub-clocks in an MLC program mode may also be used for those same sub-clocks in a first SLC program mode. However, in a second SLC program mode a different set of timing parameters may be used for that set of sub-clocks. Using the same set of timing parameters for the MLC program mode and the first SLC program mode saves storage space. However, the timing parameters for the MLC program mode may be slower than desired for SLC programming. A different set of timing parameters may be used for the second SLC program mode to provide for faster program operation. Moreover, the different set of timing parameters used for the faster SLC program mode do not require storage of a separate set of timing parameters.