公开(公告)号：US20190237142A1

公开(公告)日：2019-08-01

申请号：US16382034

申请日：2019-04-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C16/04 ,  H01L27/11517 ,  G06N3/04

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines.

公开(公告)号：US20190172942A1

公开(公告)日：2019-06-06

申请号：US16166342

申请日：2018-10-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L27/11521

Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

公开(公告)号：US10312248B2

公开(公告)日：2019-06-04

申请号：US14935201

申请日：2015-11-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11521 ,  G11C16/14 ,  G11C16/26 ,  H01L29/423 ,  H01L29/788

Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

公开(公告)号：US20190164617A1

公开(公告)日：2019-05-30

申请号：US15826345

申请日：2017-11-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do ,  Steven Lemke ,  Santosh Hariharan ,  Stanley Hong

IPC: G11C16/34 ,  G11C16/10

Abstract: An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.

公开(公告)号：US20190148529A1

公开(公告)日：2019-05-16

申请号：US16245069

申请日：2019-01-10

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Chieng-Sheng Su ,  Nhan Do ,  Chunming Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L49/02 ,  H01L27/07 ,  H01L29/08 ,  H01L29/788

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US20190103470A1

公开(公告)日：2019-04-04

申请号：US16137399

申请日：2018-09-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Chun-Ming Chen ,  Man-Tang Wu ,  Chen-Chih Fan ,  Nhan Do

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11546 ,  H01L29/08 ,  H01L29/66 ,  H01L27/11521

Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.

公开(公告)号：US10249631B2

公开(公告)日：2019-04-02

申请号：US15945161

申请日：2018-04-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Feng Zhou ,  Jeng-Wei Yang ,  Hieu Van Tran ,  Nhan Do

IPC: H01L29/423 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11524

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

公开(公告)号：US20190080753A1

公开(公告)日：2019-03-14

申请号：US15701071

申请日：2017-09-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.

公开(公告)号：US10141321B2

公开(公告)日：2018-11-27

申请号：US15290960

申请日：2016-10-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Chun-Ming Chen ,  Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/423 ,  G11C16/04

Abstract: A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

公开(公告)号：US09972632B2

公开(公告)日：2018-05-15

申请号：US15476663

申请日：2017-03-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Nhan Do

IPC: H01L27/11521 ,  H01L29/423 ,  G11C16/10 ,  G11C16/16

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328

Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.