公开(公告)号：US08084865B2

公开(公告)日：2011-12-27

申请号：US12112588

申请日：2008-04-30

申请人： Franz Hirler ,  Walter Rieger ,  Uwe Schmalzbauer ,  Rudolf Zelsacher ,  Markus Zundel

发明人： Franz Hirler ,  Walter Rieger ,  Uwe Schmalzbauer ,  Rudolf Zelsacher ,  Markus Zundel

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L29/7813 ,  H01L21/743 ,  H01L23/535 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.

摘要翻译： 用于半导体器件的金属结构的锚定结构包括具有至少一个悬垂侧壁的锚固凹槽结构，金属结构至少部分地布置在锚定凹槽结构内。

公开(公告)号：US20110095336A1

公开(公告)日：2011-04-28

申请号：US12605751

申请日：2009-10-26

申请人： Markus Zundel ,  Franz Hirler ,  Walter Rieger

发明人： Markus Zundel ,  Franz Hirler ,  Walter Rieger

IPC分类号： H01L29/778 ,  H01L29/205

CPC分类号： H01L29/404 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

摘要： In one embodiment a lateral HEMT has a first layer, the first layer including a semiconducting material, and a second layer, the second layer including a semiconducting material and being at least partially arranged on the first layer. The lateral HEMT further has a passivation layer and a drift region, the drift region including a lateral width wd. The lateral HEMT further has at least one field plate, the at least one field plate being arranged at least partially on the passivation layer in a region of the drift region and including a lateral width wf, wherein wf

摘要翻译： 在一个实施例中，横向HEMT具有第一层，第一层包括半导体材料和第二层，第二层包括半导体材料并且至少部分地布置在第一层上。 横向HEMT还具有钝化层和漂移区域，漂移区域包括横向宽度wd。 横向HEMT还具有至少一个场板，所述至少一个场板至少部分地布置在所述漂移区域的区域中的钝化层上，并且包括横向宽度wf，其中wf

公开(公告)号：US20100264462A1

公开(公告)日：2010-10-21

申请号：US12764669

申请日：2010-04-21

申请人： Franz Hirler ,  Walter Rieger ,  Markus Zundel

发明人： Franz Hirler ,  Walter Rieger ,  Markus Zundel

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/778 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7786

摘要： A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.

摘要翻译： 公开了包括横向HEMT的半导体和用于制造横向HEMT的方法。 在一个实施例中，横向HEMT具有衬底和第一层，其中第一层具有第一导电类型的半导体材料并且至少部分地布置在衬底上。 此外，横向HEMT具有第二层，其中第二层具有半导体材料并且至少部分地布置在第一层上。 此外，横向HEMT具有第三层，其中第三层具有与第一导电类型互补的第二导电类型的半导体材料，并且至少部分地布置在第一层中。

公开(公告)号：US20090166729A1

公开(公告)日：2009-07-02

申请号：US11965387

申请日：2007-12-27

申请人： Markus Zundel ,  Franz Hirler ,  Armin Willmeroth

发明人： Markus Zundel ,  Franz Hirler ,  Armin Willmeroth

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095

摘要： A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger then a breakdown charge amount at breakdown voltage.

摘要翻译： 公开了一种具有轻掺杂漂移和缓冲层的功率半导体元件。 一个实施例具有在第一导电类型的深阱区之下并且在第二导电类型的轻掺杂漂移和缓冲层之间并且在深阱区之间。 漂移和缓冲层在半导体衬底的相邻表面上的漏极接触层和最深阱区的底部之间具有至少等于深阱区域之间的最小横向距离的最小垂直延伸。 也可以确定垂直延伸，使得漂移缓冲层中的每单位面积的掺杂剂的总量大于击穿电压时的击穿电荷量。

公开(公告)号：US07211860B2

公开(公告)日：2007-05-01

申请号：US10857353

申请日：2004-05-28

申请人： Markus Zundel ,  Franz Hirler

发明人： Markus Zundel ,  Franz Hirler

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7831

摘要： In the case of the semiconductor component (1) according to the invention, the source regions (S), the body regions (B) and, if appropriate, the body contact regions (Bk) are in each case arranged in mesa regions (M) of adjacent trenches (30). In the edge region (R) of the cell array (Z) the insulation (GOX, FOX) of the underlying trench structures (30) by an insulating oxide layer (FOX) is comparatively thick and formed in the form of a field oxide (FOX) or thick oxide (FOX).

摘要翻译： 在根据本发明的半导体部件（1）的情况下，源极区域（S），主体区域（B）以及适当时的体接触区域（Bk）分别布置在台面区域（M ）相邻的沟槽（30）。 在单元阵列（Z）的边缘区域（R）中，通过绝缘氧化物层（FOX）的下面的沟槽结构（30）的绝缘（GOX，FOX）相对较厚并且形成为场氧化物 FOX）或厚氧化物（FOX）。

公开(公告)号：US06911693B2

公开(公告)日：2005-06-28

申请号：US10446600

申请日：2003-05-28

申请人： Markus Zundel ,  Franz Hirler

发明人： Markus Zundel ,  Franz Hirler

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/00

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368

摘要： In order to form a MOS transistor device with a particularly low on resistance with a good avalanche strength at the same time, it is proposed to define the position and/or the configuration of avalanche breakdown regions by a variation and/or a course of the width and/or of the depth of the respective trench structure and/or of the respective mesa regions.

摘要翻译： 为了形成具有特别低的导通电阻并且同时具有良好的雪崩强度的MOS晶体管器件，建议通过变化和/或过程来定义雪崩击穿区域的位置和/或构造 宽度和/或各个沟槽结构和/或相应的台面区域的深度。

公开(公告)号：US06882004B2

公开(公告)日：2005-04-19

申请号：US10282971

申请日：2002-10-29

申请人： Markus Zundel ,  Franz Hirler

发明人： Markus Zundel ,  Franz Hirler

IPC分类号： H01L21/336 ,  H01L23/485 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L24/02 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/05042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor component has a minimal size and area requirement. The semiconductor component is formed in a trench with wall regions and a bottom region. Terminal regions for the electrical connection of first and second contact regions (S, B) are formed at least partly within the trench (30).

摘要翻译： 半导体元件具有最小的尺寸和面积要求。 半导体部件形成在具有壁区域和底部区域的沟槽中。 至少部分地在沟槽（30）内形成用于第一和第二接触区域（S，B）的电连接的端子区域。

公开(公告)号：US08779506B2

公开(公告)日：2014-07-15

申请号：US12987852

申请日：2011-01-10

申请人： Markus Zundel ,  Franz Hirler ,  Norbert Krischke

发明人： Markus Zundel ,  Franz Hirler ,  Norbert Krischke

IPC分类号： H01L27/06

CPC分类号： H01L27/0733 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/32105 ,  H01L21/743 ,  H01L21/823437 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7825 ,  H01L29/945

摘要： Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

摘要翻译： 公开了一种用于制造半导体元件布置的半导体元件布置和方法。 该方法包括产生沟槽晶体管结构，其中至少一个沟槽设置在半导体本体中，并且至少一个栅电极设置在至少一个沟槽中。 电极结构设置在至少一个另外的沟槽中并且包括至少一个电极。 晶体管结构的至少一个沟槽和至少一个另外的沟槽通过公共工艺步骤产生。 此外，电极结构的至少一个电极和栅电极通过常规的工艺步骤制造。

公开(公告)号：US20130240985A1

公开(公告)日：2013-09-19

申请号：US13420768

申请日：2012-03-15

申请人： Franz Hirler ,  Markus Zundel

发明人： Franz Hirler ,  Markus Zundel

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734

摘要： A semiconductor device includes a trench region extending into a drift zone of a semiconductor body from a surface. The semiconductor device further includes a dielectric structure including a first step and a second step along a lateral side of the trench region. The semiconductor device further includes an auxiliary structure of a first conductivity type between the first step and the second step, a gate electrode in the trench region and a body region of a second conductivity type other than the first conductivity type of the drift zone. The auxiliary structure adjoins each one of the drift zone, the body region and the dielectric structure.

摘要翻译： 半导体器件包括从表面延伸到半导体本体的漂移区的沟槽区域。 半导体器件还包括电介质结构，其包括沿沟槽区域的横向侧的第一步骤和第二步骤。 半导体器件还包括在第一步骤和第二步骤之间的第一导电类型的辅助结构，沟槽区域中的栅极电极和除漂移区域的第一导电类型之外的第二导电类型的体区域。 辅助结构邻接漂移区，体区和电介质结构中的每一个。

公开(公告)号：US20110294289A1

公开(公告)日：2011-12-01

申请号：US12953230

申请日：2010-11-23

申请人： Walter Reiger ,  Paul Ganitzer ,  Oliver Haeberlen ,  Franz Hirler ,  Markus Zundel ,  Rudolf Zelsacher ,  Erwin Bacher

发明人： Walter Reiger ,  Paul Ganitzer ,  Oliver Haeberlen ,  Franz Hirler ,  Markus Zundel ,  Rudolf Zelsacher ,  Erwin Bacher

IPC分类号： H01L21/768

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397

摘要： A method for producing a connection electrode for a first and second adjacent and complementarily doped semiconductor zones includes a step of producing a trench extending through the first semiconductor zone into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench. The method also includes producing a first connection zone in the first semiconductor zone by implanting dopant atoms into the sidewalls at least at a first angle. The method further includes producing a second connection zone in the second semiconductor zone by implanting dopant atoms at least at a second, different angle. The method also includes depositing an electrode layer at least onto the sidewalls and the bottom of the trench for the purpose of producing the connection electrode.

摘要翻译： 一种用于制造用于第一和第二相邻和互补掺杂的半导体区的连接电极的方法包括以下步骤：产生延伸穿过第一半导体区进入第二半导体区的沟槽，使得第一半导体区在 沟槽和第二半导体区域至少在沟槽的底部被覆盖。 该方法还包括通过至少以第一角度将掺杂剂原子注入到侧壁中来在第一半导体区域中产生第一连接区域。 该方法还包括通过至少以不同的角度注入掺杂剂原子来在第二半导体区域中产生第二连接区域。 该方法还包括至少将电极层沉积到沟槽的侧壁和底部上以产生连接电极。