公开(公告)号：US20060138535A1

公开(公告)日：2006-06-29

申请号：US11362150

申请日：2006-02-27

申请人： Syotaro Ono ,  Yusuke Kawaguchi ,  Akio Nakagawa

发明人： Syotaro Ono ,  Yusuke Kawaguchi ,  Akio Nakagawa

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/267 ,  H01L29/42368 ,  H01L29/4933

摘要： A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.

摘要翻译： 垂直MOSFET包括形成在漏极区域上的基极区域和形成在基极区域中的源极区域。 沟槽形成为从源极区域的表面延伸并且穿透源极区域并且具有深度以到达漏极区域附近的部分。 在沟槽的侧壁和底部形成栅极绝缘膜，并且在沟槽中形成栅电极。 基极区域的杂质浓度分布在源极区域和基极区域之间的界面附近的部分具有第一峰值，第二峰值形成在基极区域和漏极区域之间的界面附近的部分，并且较低 比第一个高峰。 基于第一峰确定阈值电压，并且基于第二峰确定剂量。

公开(公告)号：US07045426B2

公开(公告)日：2006-05-16

申请号：US10826259

申请日：2004-04-19

申请人： Syotaro Ono ,  Yusuke Kawaguchi

发明人： Syotaro Ono ,  Yusuke Kawaguchi

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7828

摘要： A power MOSFET comprising a drain layer of a first conductivity type, a drift layer of the first conductivity type provided on the drain layer, a base layer of a first or a second conductivity type provided on the drift layer, a source region of the first conductivity type provided on the base layer, a gate insulating film formed on an inner wall surface of a trench penetrating the base layer and reaching at the drift layer, and a gate electrode provided on the gate insulating film inside the trench, wherein the gate insulating film is formed such that a portion thereof adjacent to the drift layer is thicker than a portion thereof adjacent to the base layer, and the drift layer has an impurity concentration gradient higher in the vicinity of the drain layer and lower in the vicinity of the source region along a depth direction of trench.

摘要翻译： 一种功率MOSFET，包括第一导电类型的漏极层，设置在漏极层上的第一导电类型的漂移层，设置在漂移层上的第一或第二导电类型的基极层，第一导电类型的源极区域 设置在基底层上的导电类型，形成在穿过基底层并到达漂移层的沟槽的内壁表面上的栅极绝缘膜，以及设置在沟槽内部的栅极绝缘膜上的栅电极，其中栅极绝缘 膜形成为使得其与漂移层相邻的部分比与基底层相邻的部分厚，并且漂移层在漏极层附近具有较高的杂质浓度梯度，并且在源极附近较低 区域沿着沟槽的深度方向。

公开(公告)号：US20060081920A1

公开(公告)日：2006-04-20

申请号：US11245204

申请日：2005-10-07

申请人： Kazutoshi Nakamura ,  Syotaro Ono

发明人： Kazutoshi Nakamura ,  Syotaro Ono

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66734

摘要： A semiconductor device includes: a semiconductor substrate of the first-type; a semiconductor region of the first-type formed on the substrate; a gate electrode a part of which is present within a trench selectively formed in part of the semiconductor region, and an extended top-end to have a wide width via a stepped-portion; a gate insulating-film formed between the trench and the gate electrode along a wall surface of the trench; a base layer of the second-type on the region via the film to enclose a side-wall except a bottom of the trench; a source region of the first-type adjacent to the film outside the trench in the vicinity of a top surface of the base layer; and an insulating-film formed partially between a bottom-surface of the top-end and a top-surface of the source region and formed to have a thickness larger than that of the gate insulating-film within the trench.

摘要翻译： 半导体器件包括：第一类型的半导体衬底; 在基板上形成第一类型的半导体区域; 栅极电极，其一部分存在于在半导体区域的一部分中选择性地形成的沟槽中，并且延伸的顶端经由阶梯部分具有宽的宽度; 栅沟绝缘膜，沿着沟槽的壁表面形成在沟槽和栅电极之间; 经由膜在该区域上的第二类型的基底层以包围沟槽底部以外的侧壁; 所述第一类型的源极区域在所述基底层的顶表面附近与所述沟槽外部的膜相邻; 以及部分地形成在顶部的底表面和源极区的顶表面之间并且形成为具有比沟槽内的栅极绝缘膜的厚度大的厚度的绝缘膜。

公开(公告)号：US06720618B2

公开(公告)日：2004-04-13

申请号：US10055947

申请日：2002-01-28

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Syotaro Ono ,  Shinichi Hodama ,  Akio Nakagawa

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Syotaro Ono ,  Shinichi Hodama ,  Akio Nakagawa

IPC分类号： H01L2976

CPC分类号： H01L21/26513 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41 ,  H01L29/4175 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7835

摘要： A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

摘要翻译： 一种功率MOSFET器件，包括第一导电类型的低电阻衬底，形成在低电阻衬底上的第一导电类型的高电阻外延层，形成在高电阻外延表面区域中的第二导电类型的基极层 形成在基底层的表面区域中的第一导电类型的源极区域，形成在基极层的表面上以与源极区域接触的栅极绝缘膜，形成在栅极绝缘膜上的栅电极， 以及形成在所述高电阻外延层的与所述源极区域和所述栅极电极相反的表面上的所述第一导电类型的LDD层，其中所述LDD层和所述低电阻衬底通过所述高电阻外延层彼此连接 。

公开(公告)号：US07564097B2

公开(公告)日：2009-07-21

申请号：US11740045

申请日：2007-04-25

申请人： Syotaro Ono ,  Akio Nakagawa ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

发明人： Syotaro Ono ,  Akio Nakagawa ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/1095

摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.

摘要翻译： 公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

公开(公告)号：US20060231894A1

公开(公告)日：2006-10-19

申请号：US11405672

申请日：2006-04-18

申请人： Mitsuhiko Kitagawa ,  Takashi Nishimura ,  Yusuke Kawaguchi ,  Syotaro Ono

发明人： Mitsuhiko Kitagawa ,  Takashi Nishimura ,  Yusuke Kawaguchi ,  Syotaro Ono

IPC分类号： H01L27/12

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4933 ,  H01L29/7397 ,  H01L29/7824 ,  H01L29/7831 ,  H01L29/78603 ,  H01L29/78624

摘要： A transistor comprises: an insulating layer; a semiconductor layer provided on a major surface of the insulating layer; a gate insulating layer provided on the base region; and a gate electrode provided on the gate insulating layer. The semiconductor layer has a source portion having a plurality of source regions of a first conductivity type and a plurality of base contact regions of a second conductivity type, the source regions being alternated with the base contact regions, a drain portion of the first conductivity type, and a base region of the second conductivity type provided between the source portion and the drain portion, the base region being in contact with the source regions and the base contact regions. A junction between the source regions and the base region is closer to the drain portion side than a junction between the base contact regions and the base region.

公开(公告)号：US07061048B2

公开(公告)日：2006-06-13

申请号：US10790137

申请日：2004-03-02

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Syotaro Ono ,  Shinichi Hodama ,  Akio Nakagawa

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Syotaro Ono ,  Shinichi Hodama ,  Akio Nakagawa

IPC分类号： H01L27/96

CPC分类号： H01L21/26513 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41 ,  H01L29/4175 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7835

摘要： A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

公开(公告)号：US20050287744A1

公开(公告)日：2005-12-29

申请号：US11157908

申请日：2005-06-22

申请人： Syotaro Ono ,  Yusuke Kawaguchi ,  Akio Nakagawa

发明人： Syotaro Ono ,  Yusuke Kawaguchi ,  Akio Nakagawa

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/76 ,  H01L29/78 ,  H01L29/872 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/7806 ,  H01L29/872

摘要： A semiconductor device has a plurality of pillars formed by filling a poly-silicon via an insulating layer in a plurality of trenches arranged substantially in parallel at certain intervals, n+-semiconductor regions and p+-semiconductor regions which are formed between partial pillars among the plurality of pillars and alternately formed along a direction where the pillars extend, n−-semiconductor regions arranged between the other partial neighboring pillars among the plurality of pillars and a first metal layer which makes a schottky contact on an upper face of the n−-semiconductor regions.

摘要翻译： 半导体器件具有通过多个沟槽中的绝缘层填充多晶硅形成的多个柱，所述多个沟槽基本上以一定间隔平行设置，n + + - 半导体区域和p + 在多个柱之间的部分柱之间形成并且沿着柱延伸的方向交替形成的半导体区域，其间布置在其中的相邻部分相邻柱之间的半导体区域 多个柱状物以及在第n个半导体区域的上表面上形成肖特基接触的第一金属层。

公开(公告)号：US20050056890A1

公开(公告)日：2005-03-17

申请号：US10957692

申请日：2004-10-05

申请人： Norio Yasuhara ,  Syotaro Ono ,  Kazutoshi Nakamura ,  Yusuke Kawaguchi ,  Shinichi Hodama ,  Akio Nakagawa

发明人： Norio Yasuhara ,  Syotaro Ono ,  Kazutoshi Nakamura ,  Yusuke Kawaguchi ,  Shinichi Hodama ,  Akio Nakagawa

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/402 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

摘要翻译： 半导体器件包括具有第一导电类型的第一半导体区域，形成在第一半导体区域上并且具有第一导电类型的第二半导体区域，形成在第二半导体区域的表面中并具有第二导电类型的第三半导体区域 形成在第二半导体区域的表面上并具有第二导电类型的第四半导体区域以及形成在第二和第四半导体区域上的栅极结构。 半导体器件还包括布置在从第四半导体区域的表面延伸到第一半导体区域的沟槽中的导电构件，沟槽具有与栅极结构的侧壁表面齐平的一个侧壁表面。

公开(公告)号：US20050029586A1

公开(公告)日：2005-02-10

申请号：US10682111

申请日：2003-10-10

申请人： Syotaro Ono ,  Yusuke Kawaguchi ,  Akio Nakagawa

发明人： Syotaro Ono ,  Yusuke Kawaguchi ,  Akio Nakagawa

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/267 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/267 ,  H01L29/42368 ,  H01L29/4933

摘要： A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.

摘要翻译： 垂直MOSFET包括形成在漏极区域上的基极区域和形成在基极区域中的源极区域。 沟槽形成为从源极区域的表面延伸并且穿透源极区域并且具有深度以到达漏极区域附近的部分。 在沟槽的侧壁和底部形成栅极绝缘膜，并且在沟槽中形成栅电极。 基极区域的杂质浓度分布在源极区域和基极区域之间的界面附近的部分具有第一峰值，第二峰值形成在基极区域和漏极区域之间的界面附近的部分，并且较低 比第一个高峰。 基于第一峰确定阈值电压，并且基于第二峰确定剂量。