公开(公告)号：US20050025035A1

公开(公告)日：2005-02-03

申请号：US10878657

申请日：2004-06-29

申请人： Tsukasa Nakai ,  Sumio Ashida ,  Keiichiro Yusu ,  Takayuki Tsukamoto ,  Noritake Oomachi ,  Naomasa Nakamura ,  Urara Ichihara

发明人： Tsukasa Nakai ,  Sumio Ashida ,  Keiichiro Yusu ,  Takayuki Tsukamoto ,  Noritake Oomachi ,  Naomasa Nakamura ,  Urara Ichihara

IPC分类号： G11B7/254 ,  G11B7/241 ,  G11B7/243 ,  G11B7/257 ,  G11B7/24

CPC分类号： G11B7/252 ,  G11B7/24038 ,  G11B7/243 ,  G11B7/2437 ,  G11B7/2534 ,  G11B7/257 ,  G11B7/2578 ,  G11B7/259 ,  G11B2007/24312 ,  G11B2007/24314 ,  G11B2007/24316 ,  G11B2007/2571 ,  G11B2007/25711 ,  G11B2007/25715 ,  Y10T428/21

摘要： A phase-change optical recording medium has a phase-change recording film to which recording and erasure can be reversibly performed by irradiation with light, and at least one dielectric film formed of a SiOC film containing Si, O and C, and having a carbon concentration within a range of between 0.1 and 30 atomic %.

摘要翻译： 相变型光记录介质具有通过照射可逆地进行记录和擦除的相变记录膜，以及至少一个由含有Si，O和C的SiOC膜形成的电介质膜，并且具有碳 浓度在0.1至30原子％的范围内。

公开(公告)号：US06545971B1

公开(公告)日：2003-04-08

申请号：US09492117

申请日：2000-01-27

申请人： Takayuki Tsukamoto ,  Hideyuki Nishizawa ,  Akiko Hirao

发明人： Takayuki Tsukamoto ,  Hideyuki Nishizawa ,  Akiko Hirao

IPC分类号： G11B70037

CPC分类号： G11B7/246 ,  G11B7/08511 ,  G11B7/0938 ,  G11B7/24038 ,  G11B7/245 ,  G11B7/2467 ,  G11B7/2472 ,  G11B7/248 ,  G11B7/2531 ,  G11B7/26 ,  G11B2007/0013

摘要： A recording/reproducing system records/reproduces information in a three-dimensional optical recording medium wherein information is recordable at three-dimensional optional positions and wherein position reference regions having optical characteristics different from those of recordable regions are previously provided at predetermined positions, and for reproducing information recorded in the three-dimensional optical recording medium. The recording system comprises a light source, a detector, a moving mechanism, and a light intensity adjuster. The reproducing system comprises a light source, a condenser, a detector, a moving mechanism, and a reproducing device.

摘要翻译： 记录/再现系统在三维光学记录介质中记录/再现信息，其中信息可在三维可选位置记录，并且其中预先在预定位置提供具有与可记录区域不同的光学特性的位置参考区域，并且 再现记录在三维光学记录介质中的信息。 记录系统包括光源，检测器，移动机构和光强度调节器。 再现系统包括光源，冷凝器，检测器，移动机构和再现装置。

公开(公告)号：US08988925B2

公开(公告)日：2015-03-24

申请号：US13597318

申请日：2012-08-29

申请人： Reika Ichihara ,  Takayuki Tsukamoto

发明人： Reika Ichihara ,  Takayuki Tsukamoto

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C11/00 ,  G11C2013/0083

摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.

摘要翻译： 根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。 多个第二线延伸以与第一线相交。 多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。 控制电路被配置为控制施加到存储器单元的电压。 控制电路在成形操作期间向可变电阻器施加第一脉冲电压。 此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。 此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。

公开(公告)号：US20140063906A1

公开(公告)日：2014-03-06

申请号：US13722210

申请日：2012-12-20

申请人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Hiroshi Kanno ,  Takamasa Okawa

发明人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Hiroshi Kanno ,  Takamasa Okawa

IPC分类号： G11C13/00

CPC分类号： G11C13/0097 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided at each of intersections of a plurality of first lines and a plurality of second lines;and a control circuit applying a selected first line voltage to a selected first line, an adjacent unselected first line voltage which is larger than the selected first line voltage to an adjacent unselected first line, and an unselected first line voltage which is larger than the adjacent unselected first line voltage to an unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to a selected second line and an unselected second line voltage which is smaller than the selected second line voltage to an unselected second line.

摘要翻译： 根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括设置在多个第一线和多条第二线的每个交点处的多个存储单元; 以及控制电路，将所选择的第一线电压施加到所选择的第一线，相对于相邻未选择的第一线大于所选择的第一线电压的相邻未选择的第一线电压，以及大于相邻的未选择的第一线电压的未选择的第一线电压 将未选择的第一线电压提供给未选择的第一线，以及将选择的第二线电压大于所选择的第一线电压至选定的第二线，以及将小于所选择的第二线电压的未选择的第二线电压施加到未选择的第二线电压 线。

公开(公告)号：US20130229853A1

公开(公告)日：2013-09-05

申请号：US13599301

申请日：2012-08-30

申请人： Yoichi MINEMURA ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Tomonori Kurosawa ,  Mizuki Kaneko

发明人： Yoichi MINEMURA ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Tomonori Kurosawa ,  Mizuki Kaneko

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72

摘要： According to one embodiment, a semiconductor memory device includes a plurality of cell array blocks and a control circuit. The control circuit sets a selected bit line to have 0 volt, applies a first electric potential which is higher than 0 volt to a selected word line, applies a second electric potential which is higher than 0 volt and lower than the first electric potential to non-selected word lines other than the selected word line, applies a third electric potential which is 0 volt or more and lower than the second electric potential to a non-selected bit line adjacent to the selected bit line in an adjacent cell array block, applies the second electric potential to non-selected bit lines other than the non-selected bit line to which the third electric potential is applied, and changes a resistance status of the resistance variable film of the selected memory cell.

摘要翻译： 根据一个实施例，半导体存储器件包括多个单元阵列块和控制电路。 控制电路将所选择的位线设置为具有0伏特，对所选择的字线施加高于0伏的第一电位，将比第一电位高于0伏且低于第一电位的第二电位施加到非 - 除了所选字线以外的选定字线，将相邻单元阵列块中与选定位线相邻的未选位线施加0伏以上且低于第2电位的第3电位， 对除了施加了第三电位的未选位线之外的非选择位线的第二电位，并且改变所选存储单元的电阻变化膜的电阻状态。

公开(公告)号：US20130229851A1

公开(公告)日：2013-09-05

申请号：US13597814

申请日：2012-08-29

申请人： Tomonori KUROSAWA ,  Mizuki Kaneko ,  Takafumi Shimotori ,  Takayuki Tsukamoto ,  Yoichi Minemura ,  Hiroshi Kanno

发明人： Tomonori KUROSAWA ,  Mizuki Kaneko ,  Takafumi Shimotori ,  Takayuki Tsukamoto ,  Yoichi Minemura ,  Hiroshi Kanno

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0083 ,  G11C2213/72

摘要： In a memory cell array, memory cells each including a variable resistance element are arranged at crossing portions between a plurality of first wiring and a plurality of second wirings. A control circuit executes a set operation, a reset operation, and a training operation. In the set operation, a set pulse is applied to the variable resistance element to change the variable resistance element from a high resistance state to a low resistance state. In the reset operation, a reset pulse having an opposite polarity to the polarity of the set pulse is applied to the variable resistance element to change the variable resistance element from the low resistance state to the high resistance state. In the training operation, the set pulse and the reset pulse are continuously applied to the variable resistance element.

摘要翻译： 在存储单元阵列中，包括可变电阻元件的存储单元布置在多个第一布线和多个第二布线之间的交叉部分处。 控制电路执行设定操作，复位操作和训练操作。 在设定动作中，向可变电阻元件施加设定脉冲，将可变电阻元件从高电阻状态变为低电阻状态。 在复位操作中，将具有与设定脉冲的极性相反的极性的复位脉冲施加到可变电阻元件，以将可变电阻元件从低电阻状态改变为高电阻状态。 在训练操作中，将设定脉冲和复位脉冲连续施加到可变电阻元件。

公开(公告)号：US20120320662A1

公开(公告)日：2012-12-20

申请号：US13597318

申请日：2012-08-29

申请人： Reika ICHIHARA ,  Takayuki Tsukamoto

发明人： Reika ICHIHARA ,  Takayuki Tsukamoto

IPC分类号： G11C11/00

CPC分类号： G11C11/00 ,  G11C2013/0083

摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.

摘要翻译： 根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。 多个第二线延伸以与第一线相交。 多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。 控制电路被配置为控制施加到存储器单元的电压。 控制电路在成形操作期间向可变电阻器施加第一脉冲电压。 此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。 此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。

公开(公告)号：US08324606B2

公开(公告)日：2012-12-04

申请号：US12563470

申请日：2009-09-21

申请人： Takayuki Tsukamoto ,  Reika Ichihara ,  Hiroshi Kanno ,  Kenichi Murooka

发明人： Takayuki Tsukamoto ,  Reika Ichihara ,  Hiroshi Kanno ,  Kenichi Murooka

IPC分类号： H01L47/00

CPC分类号： G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2481

摘要： A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.

摘要翻译： 本发明的一个方面的电阻变化型存储器包括：构造成沿第一方向延伸的第一布线，沿与第一方向交叉的第二方向延伸的第二布线;串联电路，被配置为连接到第一和第二端 布线，包括在第一至第二布线方向上比在第二至第一方向上更加导电的非欧姆元件的串联电路和根据电阻状态的变化存储数据的电阻变化型存储元件， 能量供给电路，被配置为连接到所述第一布线以向所述第一布线供应能量，所述能量用于将所述数据存储在所述电阻变化型存储元件中;以及电容电路，被配置为包括电容元件并连接到所述第二布线 接线。

公开(公告)号：US08320158B2

公开(公告)日：2012-11-27

申请号：US12882685

申请日：2010-09-15

申请人： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue

发明人： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue

IPC分类号： G11C11/00

CPC分类号： G11C7/02 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.

摘要翻译： 一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据 极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。 在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。 复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

公开(公告)号：US08279655B2

公开(公告)日：2012-10-02

申请号：US12885013

申请日：2010-09-17

申请人： Hiroshi Kanno ,  Takayuki Tsukamoto ,  Takahiko Sasaki ,  Takafumi Shimotori

发明人： Hiroshi Kanno ,  Takayuki Tsukamoto ,  Takahiko Sasaki ,  Takafumi Shimotori

IPC分类号： G11C11/00 ,  G11C29/04

CPC分类号： G11C8/10 ,  G11C13/0007 ,  G11C13/0069 ,  G11C29/50016 ,  G11C2013/0083 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/72

摘要： According to an embodiment, there are provided a non-volatile semiconductor memory device includes: a memory cell array; a control circuit performing a series of operations to each memory cell and determining, as a defective memory cell, a memory cell whose data retention property does not satisfy a criteria, the series of operations including an operation applying a first bias to the memory cell in a forward direction, and including an operation thereafter applying a second bias to the memory cell in a reverse direction; a storage unit storing an address of the defective memory cell; and an address control unit performing a control to avoid storing data in the defective memory cell whose address is stored in the storage unit.

摘要翻译： 根据实施例，提供了一种非易失性半导体存储器件，包括：存储单元阵列; 对每个存储单元执行一系列操作的控制电路，并且确定其数据保持特性不满足标准的存储单元作为缺陷存储单元，所述一系列操作包括对存储单元施加第一偏置的操作 并且包括在相反方向上向存储单元施加第二偏置的操作; 存储单元，存储有缺陷的存储单元的地址; 以及地址控制单元，执行控制以避免将数据存储在其地址存储在存储单元中的有缺陷的存储单元中。