公开(公告)号：US06953749B2

公开(公告)日：2005-10-11

申请号：US09798404

申请日：2001-03-02

申请人： Yongjun Hu ,  Jigish D. Trivedi

发明人： Yongjun Hu ,  Jigish D. Trivedi

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76889 ,  H01L21/76895

摘要： Methods of forming refractory metal suicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure. In a preferred implementation, the silicon diffusion restricting layers are formed by exposing the substrate to nitridizing conditions which are sufficient to form a nitride-containing layer over the silicon-containing structure, and a refractory metal nitride compound within the refractory metal layer. A preferred refractory metal is titanium.

摘要翻译： 描述形成难熔金属硅化物组分的方法。 根据一个实施方案，在衬底上形成难熔金属层。 在难熔金属层之上形成含硅结构，并且在至少一些含硅结构上形成硅扩散限制层。 随后在足以使至少一些难熔金属层与至少一些含硅结构之间的反应至少部分地形成难熔金属硅化物组分的温度下进行退火。 根据本发明的一个方面，在与含硅结构上形成硅扩散限制层相同的步骤中，在难熔金属层之上或之内形成硅扩散限制层。 在优选的实施方案中，硅扩散限制层是通过将衬底暴露于足以在含硅结构上形成含氮化物层的氮化条件和难熔金属层内的难熔金属氮化物化合物而形成的。 优选的难熔金属是钛。

公开(公告)号：US06858525B2

公开(公告)日：2005-02-22

申请号：US10407957

申请日：2003-04-04

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L21/476

CPC分类号： H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.

公开(公告)号：US06790781B2

公开(公告)日：2004-09-14

申请号：US10454098

申请日：2003-06-02

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L21311

CPC分类号： H01L21/3083 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/823878

摘要： A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well region.

摘要翻译： 形成在有源器件与相同导电类型的导电阱区之间的双深度沟槽隔离结构，其包括具有第一隔离沟槽深度的第一隔间隔离结构，具有第二隔离沟槽深度的第二隔离阱隔离结构， 形成包含双深度沟槽隔离结构的双深度沟槽，该双重深度沟槽隔离结构包括第一间隔间隔离结构和第二间隔隔离结构，双深度沟槽隔离被插入在n阱导电区域和p-阱区域的边界处， 导电区域，具有第一隔离沟槽深度的第一井内隔离结构，所述第一井内隔离结构插入在位于所述n-阱区域中的一对p沟道晶体管之间，以及第二井内隔离结构 具有第二隔离沟槽深度，插入在一对n沟道晶体管之间的第二井内隔离结构 在p井区域。

公开(公告)号：US06740575B2

公开(公告)日：2004-05-25

申请号：US10290958

申请日：2002-11-07

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L2144

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L23/5254 ,  H01L27/101 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L2924/0002 ,  Y10T29/49016 ,  Y10T29/49107 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49165 ,  H01L2924/00

摘要： An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

摘要翻译： 一种反熔丝，包括具有基本上平行于第一轴线布置的多个纵向部件的底板，形成在底板上的电介质层以及具有基本平行于第二轴线布置的多个纵向部件的顶板，顶板 形成在电介质层上。 形成在顶板和底板之间的界面处的多个边缘在横跨反熔丝施加编程电压时导致局部电荷浓度的区域。 结果，在底板的角部上形成反熔丝电介质在反熔丝的编程期间增强了电场。 减少编程电压可用于对反熔丝进行编程，并且导致顶板和底板之间的导电路径很可能沿着多个边缘形成。

公开(公告)号：US06683365B1

公开(公告)日：2004-01-27

申请号：US10211476

申请日：2002-08-01

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L2900

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L23/5254 ,  H01L27/101 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L2924/0002 ,  Y10T29/49016 ,  Y10T29/49107 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49165 ,  H01L2924/00

摘要： An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

摘要翻译： 一种反熔丝，包括具有基本上平行于第一轴线布置的多个纵向部件的底板，形成在底板上的电介质层以及具有基本平行于第二轴线布置的多个纵向部件的顶板，顶板 形成在电介质层上。 形成在顶板和底板之间的界面处的多个边缘在横跨反熔丝施加编程电压时导致局部电荷浓度的区域。 结果，在底板的角部上形成反熔丝电介质在反熔丝的编程期间增强了电场。 减少编程电压可用于对反熔丝进行编程，并且导致顶板和底板之间的导电路径很可能沿着多个边缘形成。

公开(公告)号：US06576978B2

公开(公告)日：2003-06-10

申请号：US09896400

申请日：2001-06-29

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L2900

CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C17/08 ,  H01L27/0802 ,  H01L27/1112 ,  Y10S257/904 ,  Y10S438/954

摘要： The present disclosure is directed to the use of non-ion-implanted silicon oxynitride films as resistive elements. Such films have been traditionally used in semiconductor processing as antireflective coatings, but their utility as highly resistive circuit elements has heretofore not been realized. Such films find specific utility when used as the load resistors in a 4-T SRAM cell.

摘要翻译： 本公开涉及使用非离子注入的氮氧化硅膜作为电阻元件。 这种薄膜传统上用于半导体加工中作为抗反射涂层，但是它们作为高电阻电路元件的用途迄今尚未实现。 当用作4-T SRAM单元中的负载电阻时，这种电影具有特殊的用途。

公开(公告)号：US06521953B2

公开(公告)日：2003-02-18

申请号：US10116809

申请日：2002-04-04

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L2976

CPC分类号： H01L21/823878 ,  H01L21/266 ,  H01L21/823842

摘要： A method of implanting dopants into a semiconductor structure is described wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. Also semiconductor structures having two doped regions of a semiconductive material separated by a region less heavily doped than the doped regions are described.

摘要翻译： 描述了将掺杂剂注入到半导体结构中的方法，其中在注入第一掺杂剂之后并且在注入第二掺杂剂之前，光致抗蚀剂掩模的侧边缘移动。 还描述了具有由比掺杂区域重掺杂的区域分开的半导体材料的两个掺杂区域的半导体结构。

公开(公告)号：US06436805B1

公开(公告)日：2002-08-20

申请号：US09388832

申请日：1999-09-01

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L2144

CPC分类号： H01L21/32053 ,  H01L21/28518 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides methods of forming local interconnect structures for integrated circuits. A representative embodiment includes depositing a silicon source layer over a substrate having at least one topographical structure thereon. The silicon source layer preferably comprising silicon rich silicon nitride, silicon oxynitride or other silicon source having sufficient free silicon to form a silicide but not so much free silicon as to result in formation of stringers (i.e., does not comprise polysilicon). The silicon source layer is preferably deposited over an active area in the substrate and at least a portion of the topographical structure. A silicide forming material, e.g., a refractory metal, is deposited directly on selected regions of the silicon source layer and over the topographical structure. A silicide layer is made from the silicide forming material and the silicon source layer preferably by annealing the structure. The silicide layer defines a portion of the local interconnect structure, unreacted silicide forming material is removed and an interlevel dielectric is formed over the silicide layer. The interlevel dielectric includes a recess defined substantially over the active area and an electrically conductive material is deposited in the recess. The present invention also provides local interconnect structures.

摘要翻译： 本发明提供了形成用于集成电路的局部互连结构的方法。 代表性的实施例包括在其上具有至少一个形貌结构的衬底上沉积硅源层。 硅源层优选地包括富硅的氮化硅，氮氧化硅或具有足够的游离硅的其它硅源，以形成硅化物而不是太多的游离硅，从而导致桁条的形成（即不包括多晶硅）。 硅源层优选沉积在衬底中的有源区域和形貌结构的至少一部分上。 形成硅化物的材料，例如难熔金属，直接沉积在硅源层的选定区域上并且在形貌结构上。 硅化物层由硅化物形成材料和硅源层制成，优选通过退火该结构。 硅化物层限定局部互连结构的一部分，去除未反应的硅化物形成材料，并在硅化物层之上形成层间电介质。 层间电介质包括基本上在有源区域上限定的凹部，并且导电材料沉积在凹部中。 本发明还提供局部互连结构。

公开(公告)号：US6120915A

公开(公告)日：2000-09-19

申请号：US20591

申请日：1998-02-04

申请人： Yongjun Hu ,  Jigish D. Trivedi

发明人： Yongjun Hu ,  Jigish D. Trivedi

IPC分类号： H01L21/768 ,  H01L23/498 ,  B32B15/00 ,  B32B15/04 ,  B32B18/00

CPC分类号： H01L21/76895 ,  H01L21/76889 ,  H01L23/49866 ,  H01L2924/0002 ,  Y10S257/915 ,  Y10T428/12576

摘要： Methods of forming refractory metal silicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure. In a preferred implementation, the silicon diffusion restricting layers are formed by exposing the substrate to nitridizing conditions which are sufficient to form a nitride-containing layer over the silicon-containing structure, and a refractory metal nitride compound within the refractory metal layer. A preferred refractory metal is titanium.

摘要翻译： 描述形成难熔金属硅化物组分的方法。 根据一个实施方案，在衬底上形成难熔金属层。 在难熔金属层之上形成含硅结构，并且在至少一些含硅结构上形成硅扩散限制层。 随后在足以使至少一些难熔金属层与至少一些含硅结构之间的反应至少部分地形成难熔金属硅化物组分的温度下进行退火。 根据本发明的一个方面，在与含硅结构上形成硅扩散限制层相同的步骤中，在难熔金属层之上或之内形成硅扩散限制层。 在优选的实施方案中，硅扩散限制层是通过将衬底暴露于足以在含硅结构上形成含氮化物层的氮化条件和难熔金属层内的难熔金属氮化物化合物而形成的。 优选的难熔金属是钛。

公开(公告)号：US5981380A

公开(公告)日：1999-11-09

申请号：US27537

申请日：1998-02-23

申请人： Jigish D. Trivedi ,  Ravi Iyer

发明人： Jigish D. Trivedi ,  Ravi Iyer

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L29/45 ,  H01L21/70

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002

摘要： A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer comprising tungsten silicide is formed over the first barrier layer. A photoresist layer is then formed over the hard mask layer. The hard mask layer is selectively removed from above an adjacent gate stack on the semiconductor substrate using an etch that is selective to the first barrier layer. The first barrier layer is selectively removed using an etch that is selective to the hard mask layer. A silica layer is formed over the hard mask layer. A recess is formed in the silica layer that is aligned with an active area within the semiconductor substrate. The recess is filled with an electrically conductive material. A second method of forming a local interconnect structure is provided comprising forming a first barrier layer comprising sputter titanium nitride over a semiconductor substrate having a topographical structure situated upon a field oxide region within the semiconductor substrate. A first electrically conductive layer comprising tungsten is then formed over the first barrier layer using chemical vapor deposition. The first electrically conductive layer provides good step coverage over the topographical structure. A second barrier layer comprising sputtered titanium nitride is formed over the first electrically conductive layer. A hard mask layer comprising polysilicon or silica is then formed over the second barrier layer. The hard mask is selectively removed from above an adjacent gate stack on the semiconductor substrate with an etch that is selective to the second barrier layer. The second barrier layer, the first conductive layer, and the first barrier layer are selectively removed, thereby exposing the underlying gate stack on the semiconductor substrate using a chemical etch selective to the hard mask layer. A silica layer is then formed with a recess therein that is filled with an electrically conductive material to form an active area contact through the local interconnect structure.