PROCESS CONTROLLER, PROCESS CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM
    91.
    发明申请
    PROCESS CONTROLLER, PROCESS CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM 有权
    过程控制器,过程控制方法和计算机可读记录介质

    公开(公告)号:US20090192643A1

    公开(公告)日:2009-07-30

    申请号:US12354574

    申请日:2009-01-15

    IPC分类号: G06F19/00

    摘要: A process control method comprises adjusting a process condition in consideration of a performance variation among a plurality of manufacturing apparatuses, the performance variation affecting a finished shape of a pattern used to manufacture a semiconductor device, running a simulation of the finished shape under the adjusted process condition, extracting a dangerous point of the pattern affecting satisfaction from the result of the simulation, comparing a first process capability serving as a judgment standard to find whether a production schedule of the device is achieved with a second capability serving to form a dangerous pattern containing the dangerous point, and improving the second process when the second process capability is lower than the first process capability.

    摘要翻译: 一种过程控制方法包括考虑多个制造装置之间的性能变化来调整工艺条件,影响用于制造半导体器件的图案的成品形状的性能变化,在调整过程下运行成品形状的模拟 从模拟结果中提取影响满意度的模式的危险点,比较作为判断标准的第一处理能力,以确定是否实现具有第二能力的设备的生产计划,以形成含有 危险点,并且当第二处理能力低于第一处理能力时,改进第二过程。

    PATTERN GENERATION METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
    92.
    发明申请
    PATTERN GENERATION METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
    图案生成方法,计算机可读记录介质和半导体器件制造方法

    公开(公告)号:US20090186424A1

    公开(公告)日:2009-07-23

    申请号:US12354119

    申请日:2009-01-15

    IPC分类号: H01L21/00 G06F17/50

    CPC分类号: G06F17/5068 G03F1/36

    摘要: A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern and a pattern adjacent to the arbitrary pattern; correcting the first design constraint in accordance with pattern conversion by the second process, and thereby acquiring a second design constraint for the second pattern which uses, as indices, two patterns on both sides of a predetermined pattern space of the second pattern; judging whether the design pattern fulfils the second design constraint; and changing the design pattern so as to correspond to a value allowed by the second design constraint when the design constraint is not fulfilled.

    摘要翻译: 图案生成方法包括:通过第一处理获取要在过程目标胶片上形成的第一图案的第一设计约束,所述第一设计约束使用作为所述第一图案中的任意一个的图案宽度的索引,以及 任意图案之间的空间和与任意图案相邻的图案; 根据第二处理的图案转换来校正第一设计约束,从而获得第二图案的第二设计约束,该第二图案使用在第二图案的预定图案空间的两侧上的两个图案作为索引; 判断设计模式是否符合第二设计约束; 并且当不满足设计约束时,改变设计模式以对应于由第二设计约束允许的值。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING
    94.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING 有权
    半导体器件及其制造方法

    公开(公告)号:US20090014841A1

    公开(公告)日:2009-01-15

    申请号:US12169270

    申请日:2008-07-08

    IPC分类号: H01L29/06 G11C5/02

    摘要: A first region having a first pattern which includes a first minimum dimension, a second region having a second pattern which includes a second minimum dimension larger the first minimum dimension, the second region being arranged adjacent to the first region, wherein a boundary between the first region and the second region is sectioned by a width which is twice of more of a minimum dimension which exists in an adjacent region.

    摘要翻译: 具有包括第一最小尺寸的第一图案的第一区域,具有第二图案的第二区域,所述第二图案包括具有大于所述第一最小尺寸的第二最小尺寸,所述第二区域布置成与所述第一区域相邻,其中所述第一图案 区域,并且第二区域被存在于相邻区域中的最小尺寸的两倍以上的宽度分割。

    Pattern correction method, pattern correction system, mask manufacturing method, semiconductor device manufacturing method, recording medium, and designed pattern
    95.
    发明授权
    Pattern correction method, pattern correction system, mask manufacturing method, semiconductor device manufacturing method, recording medium, and designed pattern 有权
    图案校正方法,图案校正系统,掩模制造方法,半导体器件制造方法,记录介质和设计图案

    公开(公告)号:US07458057B2

    公开(公告)日:2008-11-25

    申请号:US10882217

    申请日:2004-07-02

    申请人: Toshiya Kotani

    发明人: Toshiya Kotani

    IPC分类号: G06F17/50

    CPC分类号: G03F1/36 H01J2237/31769

    摘要: According to an aspect of the invention, there is provided a pattern correction method in which a shape of a target pattern is corrected in accordance with an arrangement state between the target pattern configuring a designed pattern and a vicinity pattern disposed in the vicinity of the target pattern, the pattern correction method comprises detecting a first arrangement state between a first predetermined portion of an edge of the target pattern and the vicinity pattern, detecting a second arrangement state between a second predetermined portion of the edge of the target pattern and the vicinity pattern, determining a correction value of the edge of the target pattern based on a rule in accordance with the first and second arrangement states, and adding the correction value to the edge of the target pattern.

    摘要翻译: 根据本发明的一个方面,提供了一种图案校正方法,其中根据构成设计图案的目标图案和布置在目标附近的附近图案之间的布置状态来校正目标图案的形状 图案校正方法包括检测目标图案的边缘的第一预定部分与附近图案之间的第一布置状态,检测目标图案的边缘的第二预定部分与附近图案之间的第二布置状态 基于根据第一和第二布置状态的规则确定目标图案的边缘的校正值,并将校正值与目标图案的边缘相加。

    PATTERN CREATION METHOD, MASK MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
    96.
    发明申请
    PATTERN CREATION METHOD, MASK MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 失效
    图形创建方法,掩模制造方法和半导体器件制造方法

    公开(公告)号:US20080235650A1

    公开(公告)日:2008-09-25

    申请号:US12050764

    申请日:2008-03-18

    IPC分类号: G06F17/50

    CPC分类号: G03F1/00

    摘要: A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being most proximate to the most extreme end pattern from the second layer and converting the extracted data to a third layer, generating data of a contacting pattern which contacts both the first most proximate pattern and the most extreme end pattern in a fourth layer, generating data of a non-overlapping pattern of the contacting pattern excluding overlapping portions with the most extreme end pattern and the first most proximate pattern in a fifth layer, extracting data of a second most proximate pattern being most proximate to the non-overlapping pattern and converting the extracted data to the first layer.

    摘要翻译: 一种图案创建方法,包括在第一层上布置集成电路图案的最极端格式的数据,并且在第二层上布置不包括最末端图案的集成电路图案的数据,提取第一最接近的数据 图案最接近于来自第二层的最末端图案,并将所提取的数据转换为第三层,产生在第四层中接触第一最近图案和最末端图案的接触图案的数据,产生 接触图案的非重叠图案的数据,不包括在第五层中具有最末端图案和最前端图案和第一最近图案的重叠部分,提取最接近图案的第二最接近图案的数据,其最接近非重叠图案并且转换 提取的数据到第一层。

    Method of Forming Contact Hole Pattern in Semiconductor Integrated Circuit Device
    97.
    发明申请
    Method of Forming Contact Hole Pattern in Semiconductor Integrated Circuit Device 失效
    在半导体集成电路器件中形成接触孔图案的方法

    公开(公告)号:US20080070402A1

    公开(公告)日:2008-03-20

    申请号:US11857275

    申请日:2007-09-18

    IPC分类号: H01L21/4763 H01L21/311

    摘要: A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film and insulating layer. Etching is performed by using the resist film as a mask, thereby forming the first hole in the block film and insulating layer, and the second hole in the insulating layer. The depth of the first hole from the upper surface of the insulating layer is smaller than that of the second hole, so the first hole does not reach the semiconductor substrate.

    摘要翻译: 在包括要形成第一孔的绝缘层的区域,并且不形成第二孔的区域上形成阻挡膜,并且具有用于形成第一孔和第二孔的开口的抗蚀剂膜是 形成在阻挡膜和绝缘层上。 通过使用抗蚀剂膜作为掩模进行蚀刻,从而在阻挡膜和绝缘层中形成第一孔,并在绝缘层中形成第二孔。 绝缘层的上表面的第一孔的深度小于第二孔的深度,所以第一孔不到达半导体衬底。

    Pattern dimension correction method and verification method using OPC, mask and semiconductor device fabricated by using the correction method, and system and software product for executing the correction method
    98.
    发明授权
    Pattern dimension correction method and verification method using OPC, mask and semiconductor device fabricated by using the correction method, and system and software product for executing the correction method 失效
    使用修正方法制作的OPC,掩模和半导体器件的图案尺寸校正方法和验证方法,以及执行校正方法的系统和软件产品

    公开(公告)号:US07213226B2

    公开(公告)日:2007-05-01

    申请号:US10920397

    申请日:2004-08-18

    IPC分类号: G06F17/50

    CPC分类号: G03F1/36

    摘要: A method of correcting a finish pattern dimension by using OPC when a design pattern is formed on a wafer, including selecting and determining a first design pattern included in the design pattern; acquiring a measurement value of a first finish pattern dimension when the first design pattern is formed on a wafer; determining a first calculation model by using the first finish pattern dimension; selecting and determining a second design pattern from the design pattern except for the first design pattern; performing first simulation by using the first calculation model, and calculating a second finish pattern dimension when the second design pattern is formed on a wafer; determining a second calculation model for performing second simulation which is faster than the first simulation, by using the first and second finish pattern dimensions; and performing the second simulation by using the second calculation model, and calculating a third finish pattern dimension of a third design pattern of the design pattern except for the first and second design patterns.

    摘要翻译: 一种当在晶片上形成设计图案时通过使用OPC来校正精加工图案尺寸的方法,包括选择和确定包括在设计图案中的第一设计图案; 当在晶片上形成第一设计图案时,获取第一精加工图案尺寸的测量值; 通过使用所述第一完成图案维度来确定第一计算模型; 从除了第一设计图案之外的设计图案中选择和确定第二设计图案; 通过使用第一计算模型执行第一模拟,以及当在晶片上形成第二设计图案时计算第二精加工图案尺寸; 通过使用第一和第二完成图案尺寸,确定用于执行比第一模拟更快的第二模拟的第二计算模型; 以及通过使用所述第二计算模型执行所述第二模拟,以及计算除了所述第一和第二设计图案之外的所述设计图案的第三设计图案的第三精加工图案尺寸。

    Lithography simulation method, mask pattern preparation method, semiconductor device manufacturing method and recording medium
    99.
    发明申请
    Lithography simulation method, mask pattern preparation method, semiconductor device manufacturing method and recording medium 失效
    光刻模拟法,掩模图案制备方法,半导体器件制造方法和记录介质

    公开(公告)号:US20070019058A1

    公开(公告)日:2007-01-25

    申请号:US11485554

    申请日:2006-07-13

    IPC分类号: B41J2/385

    CPC分类号: G03F7/70433 G03F7/705

    摘要: A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern to be interested, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern to be interested and a pattern of a neighboring region, the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern to be interested; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern to be interested and the reference intensity line in the changed relative position to define an interested line width of the pattern to be interested.

    摘要翻译: 光刻模拟方法包括:获取要在基板上形成的图案的设计数据,并且掩模数据,以通过透射能量线来制备用于在基板上形成图案的潜像所使用的掩模图案; 通过计算能量射线的强度来获得图案的潜像; 至少在与感兴趣的图案对应的部分中,根据感兴趣的图案之间的距离,在潜像图像曲线和参考强度线之间的能量射线的强度的方向上的相对位置 以及相邻区域的图案,所述潜像曲线是构成所述潜像的能量射线的强度分布曲线,所述基准强度线被定义为指定所述图案的边缘的位置; 以及计算与感兴趣的图案对应的潜在图像曲线的一部分的交点与变化的相对位置中的基准强度线之间的距离,以定义感兴趣的图案的感兴趣的线宽。