公开(公告)号：US06677255B1

公开(公告)日：2004-01-13

申请号：US10230328

申请日：2002-08-29

申请人： Hsueh-Hao Shih ,  Kuang-Chao Chen

发明人： Hsueh-Hao Shih ,  Kuang-Chao Chen

IPC分类号： H01L2131

CPC分类号： H01L29/6653 ,  H01L21/28273 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/66825 ,  Y10S438/954

摘要： A method of manufacturing a semiconductor device including providing a first layer, forming a layer of stacked oxide-nitride-oxide layer over the first layer, depositing a first silicon layer over the layer of stacked oxide-nitride-oxide layer, providing a layer of photoresist over the first silicon layer, patterning and defining the photoresist layer, etching the first silicon layer and stacked oxide-nitride-oxide layer unmasked by the photoresist, removing the photoresist layer, providing a cleaning solution to the stacked oxide-nitride-oxide layer with the first silicon layer as a mask, and depositing a second layer of polysilicon over the first silicon layer to form a combined silicon layer.

摘要翻译： 一种制造半导体器件的方法，包括提供第一层，在第一层上形成层叠的氧化物 - 氮化物 - 氧化物层的层，在层叠的氧化物 - 氮化物 - 氧化物层的层上沉积第一硅层，提供层 在第一硅层上的光致抗蚀剂，图案化和限定光致抗蚀剂层，蚀刻由光致抗蚀剂未被掩模的第一硅层和层叠的氧化物 - 氮化物 - 氧化物层，去除光致抗蚀剂层，为层叠的氧化物 - 氮化物 - 氧化物层提供清洁溶液 以第一硅层作为掩模，并在第一硅层上沉积第二层多晶硅以形成组合的硅层。

公开(公告)号：US6136688A

公开(公告)日：2000-10-24

申请号：US421508

申请日：1999-10-20

申请人： Keng-Chu Lin ,  Kuang-Chao Chen ,  Rong-Wu Chien ,  Lian-Fa Hung ,  Pang-Yen Tsai ,  Ching-Chang Chang

发明人： Keng-Chu Lin ,  Kuang-Chao Chen ,  Rong-Wu Chien ,  Lian-Fa Hung ,  Pang-Yen Tsai ,  Ching-Chang Chang

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/02126 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31625 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/3185

摘要： The present invention is a method of capping with a high compressive stress oxide, a boron phospho-silicate glass (BPSG) interlayer dielectric (ILD) gapfill that has been deposited on a topographic silicon substrate, in order to eliminate the formation of cracks in subsequently deposited silicon nitride (SiN) layers, other subsequently deposited high tensile stress layers and cracks that result from other post-BPSG deposition high temperature processes.

摘要翻译： 本发明是一种用高压缩应力氧化物覆盖的方法，已经沉积在地形硅衬底上的硼磷硅酸盐玻璃（BPSG）层间电介质（ILD）间隙填料，以便于随后消除裂纹的形成 沉积的氮化硅（SiN）层，其它随后沉积的高拉伸应力层和由其他后BPSG沉积高温工艺引起的裂纹。

公开(公告)号：US5989971A

公开(公告)日：1999-11-23

申请号：US926036

申请日：1997-09-09

申请人： Tuby Tu ,  Kuang-Chao Chen

发明人： Tuby Tu ,  Kuang-Chao Chen

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/1085 ,  H01L28/82 ,  Y10S438/947 ,  Y10S438/964

摘要： A method for forming a trenched polysilicon structure can be applied to a semiconductor device. The method includes steps of: a) providing a polysilicon layer; b) forming a dielectric layer on the polysilicon layer; c) forming a rugged oxide layer on the dielectric layer; d) removing a portion of the dielectric layer which is not covered by the rugged oxide layer for exposing a corresponding portion of the polysilicon layer; e) forming a plurality of microtrenches by etching the corresponding portion of the polysilicon layer; and f) removing the rugged oxide layer and the dielectric layer to obtain the trenched polysilicon structure.

摘要翻译： 用于形成沟槽多晶硅结构的方法可以应用于半导体器件。 该方法包括以下步骤：a）提供多晶硅层; b）在所述多晶硅层上形成介电层; c）在介电层上形成粗糙的氧化物层; d）去除不被粗糙氧化物层覆盖的介电层的一部分，以暴露多晶硅层的相应部分; e）通过蚀刻多晶硅层的相应部分形成多个微通孔; 以及f）去除粗糙的氧化物层和电介质层以获得沟槽的多晶硅结构。

公开(公告)号：US5869399A

公开(公告)日：1999-02-09

申请号：US908319

申请日：1997-08-07

申请人： Tuby Tu ,  Kuang-Chao Chen

发明人： Tuby Tu ,  Kuang-Chao Chen

IPC分类号： H01L21/02 ,  H01L21/00

CPC分类号： H01L28/82

摘要： The present invention is related to a method for increasing utilzable surface area of a rugged polysilicon layer in a semiconductor device. The present method includes steps of: (a) providing a pre-grown rugged polysilicon layer which is composed of polysilicon with first dopants doped therein; (b) forming another polyslicon layer on the pre-grown rugged polysilicon layer; (c) removing a portion of the another polysilicon layer by an anisotropic etching process to expose an upper surface of the pre-grown rugged polysilicon layer; and (d) etching the resulting pre-grown rugged polysilicon layer which an etching selectivity ratio of the pre-grown rugged polysilicon layer to the another polysilicon layer being greater than one, to obtain the rugged polysilicon layer having increasing utilizable surface area. A semiconductor device containing the rugged polysilicon layer created according to the present invention can work well in a relatively dense and small semiconductor chip.

摘要翻译： 本发明涉及一种用于增加半导体器件中的凹凸多晶硅层的可利用表面积的方法。 本方法包括以下步骤：（a）提供由多晶硅组成的预生长的耐久多晶硅层，其中掺杂有第一掺杂剂; （b）在预生长的粗糙多晶硅层上形成另一个多晶硅层; （c）通过各向异性蚀刻工艺去除另一多晶硅层的一部分以暴露预生长的耐磨多晶硅层的上表面; 和（d）蚀刻所得的预生长的粗糙多晶硅层，其中预生长的耐久多晶硅层与另一多晶硅层的蚀刻选择比大于1，以获得具有增加的可用表面积的粗糙多晶硅层。 包含根据本发明制造的坚固多晶硅层的半导体器件可以在相对致密和小的半导体芯片中很好地工作。

公开(公告)号：US5869394A

公开(公告)日：1999-02-09

申请号：US741195

申请日：1996-10-29

申请人： Kuang-Chao Chen ,  Tuby Tu

发明人： Kuang-Chao Chen ,  Tuby Tu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76829

摘要： A method for forming a planarization layer on a semiconductor device including the steps of first providing a substrate, then depositing a layer of a silicon-rich oxide material, then forming metal interconnects on the silicon-rich oxide layer, and depositing a TEOS-ozone oxide layer over the metal interconnects and the silicon-rich oxide layer such that a substantially planar surface is obtained.

摘要翻译： 一种在半导体器件上形成平坦化层的方法，包括以下步骤：首先提供衬底，然后沉积富硅氧化物材料层，然后在富硅氧化物层上形成金属互连，并沉积TEOS-臭氧 金属互连上的氧化物层和富硅氧化物层，使得获得基本平坦的表面。

公开(公告)号：US5366850A

公开(公告)日：1994-11-22

申请号：US46776

申请日：1993-04-14

申请人： Kuang-Chao Chen ,  Shaw-Tzeng Hsia

发明人： Kuang-Chao Chen ,  Shaw-Tzeng Hsia

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L23/532 ,  G03F7/26

CPC分类号： H01L21/76838 ,  H01L21/31055 ,  H01L21/76819 ,  H01L23/53223 ,  H01L2924/0002

摘要： A passivation layer is provided over a conductive layer for contacting the active elements of semiconductor device structures in and on a semiconductor substrate. The passivation and conductive layers are patterned simultaneously. A thin oxide layer is deposited over the patterned conductive and passivation layers. The thin oxide layer is covered with a spin-on-glass layer to fill the valleys of the patterned conductive and passivation layers. The spin-on-glass layer is cured and then partially blanket anisotropically etched through its thickness and through the thin oxide layer to the underlying passivation layer at its highest point leaving spin-on-glass layer portions in the valleys. A top dielectric layer is deposited over the spin-on-glass layer to complete the planarization. Alternatively, an anisotropic oxide is deposited over patterned conductive lines of an integrated circuit. This anisotropic oxide deposits preferentially on the horizontal surfaces and relatively little on the vertical surfaces. The anisotropic oxide layer is covered with a spin-on-glass layer to fill the valleys of the patterned conductive layer. The spin-on-glass layer is cured and then partially blanket anisotropically etched through its thickness to the underlying anisotropic layer at its lowest point leaving spin-on-glass layer portions in the valleys. A top dielectric layer is deposited over the spin-on-glass layer to complete the planarization.

摘要翻译： 钝化层设置在导电层上，用于接触半导体衬底中和半导体衬底上的半导体器件结构的有源元件。 钝化层和导电层同时被图案化。 在图案化的导电和钝化层上沉积薄的氧化物层。 薄的氧化物层被旋涂玻璃层覆盖以填充图案化的导电和钝化层的谷。 固化旋涂玻璃层，然后通过其厚度进行各向异性蚀刻，然后通过其厚度通过薄氧化物层将其部分地覆盖到其最高点处的下面的钝化层，从而在山谷中留下旋涂玻璃层部分。 顶部电介质层沉积在旋涂玻璃层上以完成平坦化。 或者，各向异性氧化物沉积在集成电路的图案化导电线上。 这种各向异性的氧化物优先沉积在水平表面上并且在垂直表面上相对较少地沉积。 各向异性氧化物层被旋涂玻璃层覆盖以填充图案化导电层的谷。 固化旋涂玻璃层，然后将其厚度各向异性地部分地覆盖在其最低点处的底层各向异性层，从而在山谷中留下旋涂玻璃层部分。 顶部电介质层沉积在旋涂玻璃层上以完成平坦化。

公开(公告)号：US5286675A

公开(公告)日：1994-02-15

申请号：US46780

申请日：1993-04-14

申请人： Kuang-Chao Chen ,  Shaw-Tzeng Hsia

发明人： Kuang-Chao Chen ,  Shaw-Tzeng Hsia

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76885 ,  H01L21/76882

摘要： A new method of completing a tungsten contact is described. An insulator layer is formed over device structures in and on a semiconductor substrate. The insulator layer is flowed to planarize the layer. The insulator layer is covered with a spin-on-glass layer which is baked and cured. Contact openings are formed through the insulator and spin-on-glass layers to the device structures and to the substrate. A nucleation layer is formed over the spin-on-glass layer and within the contact openings. A layer of tungsten is deposited over the nucleation layer. The tungsten layer is etched back, thereby leaving the tungsten layer within the contact openings and leaving some of the tungsten layer as residue overlying the spin-on-glass layer. The spin-on-glass layer is removed, thereby removing any tungsten layer residue overlying the spin-on-glass layer. The contacts are completed by an aluminum metalization.

摘要翻译： 描述了一种完成钨接触的新方法。 在半导体衬底中的半导体衬底上的器件结构之上形成绝缘体层。 使绝缘体层流动以使层平坦化。 绝缘体层被烘烤和固化的旋涂玻璃层覆盖。 通过绝缘体和旋涂玻璃层将器件结构和衬底形成接触开口。 在旋涂玻璃层上和接触开口内形成成核层。 一层钨沉积在成核层上。 钨层被回蚀刻，从而将钨层留在接触开口内，并留下一些钨层作为覆盖在旋涂玻璃层上的残留物。 除去旋涂玻璃层，从而除去覆盖旋涂玻璃层的任何钨层残留物。 触点由铝金属化完成。