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116 条记录 (耗时 0.028 秒)

    Methods and apparatus for providing an antifuse function
    92.
    发明授权
    Methods and apparatus for providing an antifuse function 有权
    提供反熔丝功能的方法和装置

    公开(公告)号：US06882027B2

    公开(公告)日：2005-04-19

    申请号：US10447018

    申请日：2003-05-28

    申请人： Axel Brintzinger ,  Carl Radens ,  William Tonti

    发明人： Axel Brintzinger ,  Carl Radens ,  William Tonti

    IPC分类号： H01L23/525 ,  H01L29/00

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.

    摘要翻译： 公开了用于提供反熔丝的方法和装置，其中反熔丝包括具有由浅沟槽隔离（STI）边界限定的有源区的半导体衬底; 栅极导体，其设置在所述半导体衬底上方并且覆盖所述STI边界的至少一部分; 设置在所述半导体衬底和所述栅极导体之间​​的电介质; 耦合到所述栅极导体的第一端子; 以及耦合到所述半导体衬底的第二端子，其中所述电介质的击穿导致所述栅极导体的区域和所述有源区域的区域之间的电连接包括基本上靠近所述STI边界。

    Method of forming an interconnect structure including a metallic interfacial layer located at a bottom via portion
    94.
    发明授权
    Method of forming an interconnect structure including a metallic interfacial layer located at a bottom via portion 有权
    形成包括位于底部通孔部分的金属界面层的互连结构的方法

    公开(公告)号：US08288276B2

    公开(公告)日：2012-10-16

    申请号：US12346040

    申请日：2008-12-30

    申请人： Chih-Chao Yang ,  Veeraraghavan S. Basker ,  William Tonti ,  Keith Kwong Hon Wong

    发明人： Chih-Chao Yang ,  Veeraraghavan S. Basker ,  William Tonti ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/76814 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.

    摘要翻译： 提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。 通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。 存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。 还提供了制造改进的电迁移电阻互连结构的方法。

    SOI CMOS compatible multiplanar capacitor
    99.
    发明授权
    SOI CMOS compatible multiplanar capacitor 有权
    SOI CMOS兼容多平面电容器

    公开(公告)号：US07728371B2

    公开(公告)日：2010-06-01

    申请号：US11857770

    申请日：2007-09-19

    申请人： Kangguo Cheng ,  Louis C Hsu ,  Jack A. Mandelman ,  William Tonti

    发明人： Kangguo Cheng ,  Louis C Hsu ,  Jack A. Mandelman ,  William Tonti

    IPC分类号： H01L27/108

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L28/60

    摘要： An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.

    摘要翻译： 孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。 环形形状的沟槽形成在掺杂顶部半导体部分周围，并填充有诸如掺杂多晶硅的导电材料。 隔离的浅沟槽隔离部分和由导电材料的环限定的掩​​埋绝缘体层的部分被蚀刻以形成空腔。 在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。 形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极，而导电材料的环，掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个 第二电极。

    SOFT ERROR REDUCTION OF CMOS CIRCUITS ON SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION USING BURIED RECOMBINATION CENTERS
    100.
    发明申请
    SOFT ERROR REDUCTION OF CMOS CIRCUITS ON SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION USING BURIED RECOMBINATION CENTERS 有权
    使用BURIED重组中心使用混合晶体方位的基板上CMOS电路的软错误减少

    公开(公告)号：US20080157202A1

    公开(公告)日：2008-07-03

    申请号：US11618346

    申请日：2006-12-29

    申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger ,  Jack A. Mandelman ,  William Tonti

    发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger ,  Jack A. Mandelman ,  William Tonti

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1083

    摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.

    摘要翻译： 公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。 由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。 可以形成多个掩埋复合层。 可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。