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115 条记录 (耗时 0.032 秒)

    Three-dimensional ferroelectric capacitor and method for manufacturing thereof as well as semiconductor memory device
    91.
    发明授权
    Three-dimensional ferroelectric capacitor and method for manufacturing thereof as well as semiconductor memory device 失效
    三维铁电电容器及其制造方法以及半导体存储器件

    公开(公告)号：US07303927B2

    公开(公告)日：2007-12-04

    申请号：US10834547

    申请日：2004-04-29

    申请人： Chiharu Isobe ,  Yoshio Sakai

    发明人： Chiharu Isobe ,  Yoshio Sakai

    IPC分类号： H01L21/20

    CPC分类号： H01L28/55 ,  H01L27/11502 ,  H01L27/11507

    摘要： A ferroelectric capacitor is provided in which the surface area of a ferroelectric thin film is expanded to increase the amount of polarization. In the ferroelectric capacitor, hemi-spherical protruding parts 31 are formed with HSG-growth on the surface of a polycrystalline silicon film 30. On the polycrystalline silicon film 30 having the hemi-spherical protruding parts 31 are sequentially laminated an adhesive layer 32, lower electrode 33, ferroelectric film 34, and upper electrode 35. The ferroelectric film 34 is shaped to overlap the shape of hemi-spherical protruding parts 31 of the polycrystalline silicon film 30, and the surface area thereof is expanded.

    摘要翻译： 提供了强电介质电容器，其中铁电薄膜的表面积被扩大以增加极化量。 在铁电电容器中，半球状突出部31在多晶硅膜30的表面上形成有HSG生长。在具有半球状突出部31的多晶硅膜30上依次层叠有粘合剂层32，下部 电极33，铁电体膜34和上部电极35.铁电体膜34成形为与多晶硅膜30的半球形突出部31的形状重叠，其表面积扩大。

    Semiconductor memory device
    92.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20070165468A1

    公开(公告)日：2007-07-19

    申请号：US11716710

    申请日：2007-03-12

    申请人： Toshiyuki Nishihara ,  Yoshio Sakai

    发明人： Toshiyuki Nishihara ,  Yoshio Sakai

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/4401 ,  G11C29/44 ,  G11C29/846 ,  G11C2029/1208

    摘要： A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.

    摘要翻译： 一种半导体存储器件，其能够通过使用有限的冗余存储器来有效地修复缺陷，同时抑制伴随着存储器的缺陷的修复的存取速度的下降，其中第一存储器阵列被分成用于每16个字线的多个存储区域， 其中区域中的有缺陷的存储器地址存储在第二存储器阵列中。 当输入用于访问第一存储器阵列的存储器地址时，从第二存储器阵列读出包括要访问的存储器的存储器区域的缺陷存储器地址。 以这种方式，存储在存储器区域中的16个字线的缺陷存储器的地址被存储在第二存储器阵列2中，因此可以存储更宽范围的有缺陷的存储器的地址。 为此，可以有效地修复随机发生的缺陷。

    Method for deriving standard 12-lead electrocardiogram, and monitoring apparatus using the same
    93.
    发明申请
    Method for deriving standard 12-lead electrocardiogram, and monitoring apparatus using the same 有权
    用于导出标准12导联心电图的方法，以及使用其的监测装置

    公开(公告)号：US20060047212A1

    公开(公告)日：2006-03-02

    申请号：US11212565

    申请日：2005-08-29

    申请人： Daming Wei ,  Yoshio Sakai

    发明人： Daming Wei ,  Yoshio Sakai

    IPC分类号： A61B5/0402

    CPC分类号： A61B5/04028 ,  A61B5/0402 ,  A61B5/0428

    摘要： Four first electrodes are attached on the vicinity of a lower right end of a right clavicle, the vicinity of a lower left end of a left clavicle, the vicinity of a position on a right anterior axillary line at the level of a right lowermost rib, a the vicinity of a position on a left anterior axillary line at the level of a left lowermost rib of a living body, so as to correspond to limb leads of a standard 12-lead electrocardiogram (ECG). Two second electrodes are attached on such positions of the living body that correspond to a lead V2 and a lead V4 of chest leads of the standard 12-lead ECG. A first ECG data set corresponding to leads I and II of the standard 12-lead EGG with the first electrodes. A second ECG data set including the leads V2 and V4 with the second electrodes. An instantaneous electromotive force vector (a heart vector) is calculated based on the first and second ECG data sets, and predetermined first lead vectors of the leads I, II, V2 and V4. A third ECG data set including leads V1, V3, V5 and V6 of the chest leads is calculated based on the heart vector-and predetermined second lead vectors of the leads V1, V3, V5 and V6. A fourth EGG data set corresponding to leads III, aVR, aVL and aVF of the standard 12-lead EGG based on the first ECG data set The standard 12-lead EGG is derived based on the first to fourth ECG data sets.

    摘要翻译： 四个第一电极附着在右锁骨的右下端附近，左锁骨左下端附近，右下腋下线位于右下肋骨附近， 在生物体的左下肋骨的水平处的左前腋细线上的位置附近，以与标准12导联心电图（ECG）的肢体引线相对应。 两个第二电极附接在对应于标准12导联ECG的胸部引线的引线V 2和引线V 4的生物体的这些位置上。 对应于具有第一电极的标准12导联EGG的引线I和II的第一ECG数据集。 包括具有第二电极的引线V 2和V 4的第二ECG数据集。 基于第一和第二ECG数据集以及引线I，II，V 2和V 4的预定的第一引导向量来计算瞬时电动势矢量（心脏矢量）。 基于引线V 1，V 3，V 5和V 6的心脏矢量和预定的第二引导矢量计算包括胸部引线的引线V 1，V 3，V 5和V 6的第三ECG数据集。 基于第一ECG数据集的与标准12导联EGG的引线III，aVR，aVL和aVF相对应的第四个EGG数据集。基于第一至第四ECG数据集导出标准的12引导EGG。

    Blood pressure measuring system
    94.
    发明授权
    Blood pressure measuring system 失效
    血压测量系统

    公开(公告)号：US5699807A

    公开(公告)日：1997-12-23

    申请号：US507709

    申请日：1995-07-26

    申请人： Jun Motogi ,  Yoshio Sakai ,  Sunao Takeda

    发明人： Jun Motogi ,  Yoshio Sakai ,  Sunao Takeda

    IPC分类号： A61B5/022 ,  A61B5/02

    CPC分类号： A61B5/02116 ,  A61B5/022 ,  A61B5/7239

    摘要： A pressure sensor gathers discrete data representing the pulse amplitude of a pulse wave signal when a cuff pressure is increased and decreased. A RAM stores the discrete data of the pulse amplitude. A CPU processes the discrete data by using a spline function, to thereby generate the data representative of a smooth continuous line passing by points of the pulse amplitude of the discrete data. This process reduces a variation of the pulse amplitude of a pulse wave signal, to thereby minimize a variation of the blood pressure values. An inflection point of the smooth continuous line is used as a diastolic blood pressure value.

    摘要翻译： 当袖带压力增加和减小时，压力传感器收集表示脉搏波信号的脉冲幅度的离散数据。 RAM存储脉冲幅度的离散数据。 CPU通过使用样条函数处理离散数据，从而生成表示通过离散数据的脉冲幅度的点的平滑连续线的数据。 该过程减少了脉搏波信号的脉冲幅度的变化，从而使血压值的变化最小化。 平滑连续线的拐点被用作舒张血压值。

    Semiconductor integrated circuit device
    95.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5646423A

    公开(公告)日：1997-07-08

    申请号：US470451

    申请日：1995-06-06

    申请人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

    发明人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/04 ,  H01L31/036

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

    摘要： A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type and p-type polycrystalline silicon films, respectively, and the drain regions of the first and second p-channel load MISFETs are electrically connected to the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. The polycrystalline silicon gate electrodes of the first and second load MISFETs are respectively electrically connected to the drain regions of the second and first drive MISFETs in each memory cell of the SRAM, furthermore.

    摘要翻译： 公开了SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFETS之上。 存储单元的每个负载MISFET由形成在同一多晶硅膜内的源极，漏极和沟道区域以及由与驱动MISFET不同的导电膜构成的栅电极组成。 在具有这种堆叠布置的存储单元中，其每个负载MISFET的源极（漏极）区域和栅电极被图案化以具有彼此重叠的关系，从而增加与每个存储单元存储节点相关联的有效电容 。 驱动和负载MISFET两者的栅电极分别由n型和p型多晶硅膜形成，并且第一和第二p沟道负载MISFET的漏极区域电连接到第一 和第二n沟道驱动MISFET分别通过单独的多晶硅膜。 此外，第一和第二负载MISFET的多晶硅栅电极分别电连接到SRAM的每个存储单元中的第二和第一驱动MISFET的漏极区。

    Semiconductor memory device
    96.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5591998A

    公开(公告)日：1997-01-07

    申请号：US443106

    申请日：1995-05-17

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

    CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

    Semiconductor memory device having stacked capacitors
    97.
    发明授权
    Semiconductor memory device having stacked capacitors 失效
    具有层叠电容器的半导体存储器件

    公开(公告)号：US5583358A

    公开(公告)日：1996-12-10

    申请号：US324352

    申请日：1994-10-17

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

    CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

    Group control elevator system for automatically adjusting elevator operation based on a evaluation function
    98.
    发明授权
    Group control elevator system for automatically adjusting elevator operation based on a evaluation function 失效
    组控电梯系统，用于根据评估功能自动调整电梯运行

    公开(公告)号：US5409085A

    公开(公告)日：1995-04-25

    申请号：US156980

    申请日：1993-11-24

    申请人： Atsuya Fujino ,  Toshimitsu Tobita ,  Hiromi Inaba ,  Kiyoshi Nakamura ,  Yoshio Sakai ,  Kenji Yoneda ,  Hiroaki Yamani

    发明人： Atsuya Fujino ,  Toshimitsu Tobita ,  Hiromi Inaba ,  Kiyoshi Nakamura ,  Yoshio Sakai ,  Kenji Yoneda ,  Hiroaki Yamani

    IPC分类号： B66B1/20 ,  B66B1/18 ,  B66B1/24

    CPC分类号： B66B1/2458 ,  B66B2201/102 ,  B66B2201/211 ,  B66B2201/402 ,  B66B2201/403

    摘要： The present invention relates to a group control elevator system which has been adjusted to operate in response to a state of utilizing elevator cars. In a group control elevator system which carries out a control of allocating elevator cars to elevator car calls for serving many floors by using an evaluation function having a plurality of variable parameters, targets for elevator control performance are inputted, a traffic flow to which elevator car demand belongs is judged, variable parameters to be adjusted which have been set in advance for each combination of said targets and traffic flows are stored, stored variable parameters are adjusted, adjustment sequence of variable parameters to be adjusted is stored, and a plurality of variable parameters are sequentially adjusted according to the stored sequence. By the above arrangement, only desired parameters to be adjusted are selected and adjusted out of a plurality of variable parameters for desired targets and traffic flows. Accordingly, an increase in time required for adjustment can be restricted even if there has been an increase in the number of variable parameters to be adjusted.

    摘要翻译： 本发明涉及一种已经被调整为响应于利用电梯轿厢的状态而操作的组控制电梯系统。 在通过使用具有多个可变参数的评价函数来执行将电梯轿厢分配给用于服务多层的电梯轿厢呼叫的控制的组控制电梯系统中，输入电梯控制性能的目标，电梯轿厢 对所要求的属性进行判断，对于所述目标和交通流量的每个组合预先设定的要调整的可变参数被存储，存储可变参数，存储可调参数的调整顺序和多个变量 根据存储的顺序依次调整参数。 通过上述布置，仅针对期望的目标和业务流量从多个可变参数中选择和调整要调整的期望参数。 因此，即使调整的可变参数的数量增加，也可以限制调整所需的时间的增加。