公开(公告)号：US08929139B2

公开(公告)日：2015-01-06

申请号：US13308301

申请日：2011-11-30

申请人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

发明人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/14

CPC分类号： G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block.

摘要翻译： 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，描述了一种闪存器件，其包括包括多个存储器单元块的存储器阵列。 该装置还包括执行泄漏抑制处理的控制器。 泄漏抑制过程包括确定给定的存储单元块包括一个或多个过擦除存储器单元。 在确定时，泄漏抑制处理还包括执行软程序操作以增加给定块中的被擦除的存储器单元的阈值电压。

公开(公告)号：US08891312B2

公开(公告)日：2014-11-18

申请号：US13453312

申请日：2012-04-23

申请人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/16 ,  G11C16/344

摘要： Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

摘要翻译： 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

公开(公告)号：US08723559B2

公开(公告)日：2014-05-13

申请号：US13603815

申请日：2012-09-05

申请人： Chang-Ting Chen ,  Chin-Hung Chang ,  Shang-Chi Yang ,  Kuan-Ming Lu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chang-Ting Chen ,  Chin-Hung Chang ,  Shang-Chi Yang ,  Kuan-Ming Lu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.

摘要翻译： 可用作字线驱动器的电路包括响应于控制节点上的电压而切换的驱动器，以及向控制节点提供电压的电路。 向控制节点施加电压的电路提供趋向于将控制节点拉至第一源电压的第一静态电流，并且响应于选择驱动器的信号提供战斗电流脉冲以将控制节点向下拉到第二静态电流 源电压，克服第一静电流。 此外，电路在选择驱动器的信号转变时提供上拉升压电流，该信号使关闭电流消失，并且向控制节点施加升压电流脉冲，以帮助快速将控制节点拉到第一源电压 。

公开(公告)号：US20140062543A1

公开(公告)日：2014-03-06

申请号：US13603815

申请日：2012-09-05

申请人： Chang-Ting Chen ,  Chin-Hung Chang ,  Shang-Chi Yang ,  Kuan-Ming Lu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Chang-Ting Chen ,  Chin-Hung Chang ,  Shang-Chi Yang ,  Kuan-Ming Lu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： H03K3/00

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.

摘要翻译： 可用作字线驱动器的电路包括响应于控制节点上的电压而切换的驱动器，以及向控制节点提供电压的电路。 向控制节点施加电压的电路提供趋向于将控制节点拉至第一源电压的第一静态电流，并且响应于选择驱动器的信号提供战斗电流脉冲以将控制节点向下拉到第二静态电流 源电压，克服第一静电流。 此外，电路在选择驱动器的信号转变时提供上拉升压电流，该信号使关闭电流消失，并且向控制节点施加升压电流脉冲，以帮助快速将控制节点拉到第一源电压 。

公开(公告)号：US20140028367A1

公开(公告)日：2014-01-30

申请号：US13556579

申请日：2012-07-24

申请人： YU-MENG CHAUNG ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

发明人： YU-MENG CHAUNG ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC分类号： H03K5/06

CPC分类号： H03K17/145 ,  H03K19/00384 ,  H03K2005/00026

摘要： An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

摘要翻译： 集成电路包括输出缓冲器和控制电路。 输出缓冲器具有信号输入，信号输出和一组控制输入。 输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。 控制电路连接到输出缓冲器的一组控制输入。 控制电路使用第一和第二定时信号来产生控制信号，并且包括产生具有参考延迟的第一定时信号的参考延迟电路，以及延迟仿真电路，其产生与第二定时信号相关的仿真延迟 输出缓冲区延迟。

公开(公告)号：US08638636B2

公开(公告)日：2014-01-28

申请号：US12816960

申请日：2010-06-16

申请人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C8/00

CPC分类号： G11C16/16

摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.

摘要翻译： 该技术的一个实施例是一种装置，存储器集成电路。 存储器集成电路具有字线地址解码电路。 该电路允许选择单个字线以具有擦除电压。 解码器电路包括反相器和逻辑。 逆变器具有输入和控制字线的输出以执行擦除操作。 输入的电压范围在第一参考电压和第二电压基准之间延伸。 电压基准的示例是电压源和地。 在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。 解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

公开(公告)号：US08630128B2

公开(公告)日：2014-01-14

申请号：US13523060

申请日：2012-06-14

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

摘要翻译： 集成电路包括串行外设接口存储器件。 在一个实施例中，存储器件包括时钟信号，多个引脚和配置寄存器。 在一个实施例中，配置寄存器包括等待周期计数。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时向存储器件发送读取地址。 在一个实施例中，读地址至少包括第一地址位和第二地址位，第一地址位使用第一输入/输出引脚发送，第二地址位使用第二输入/输出引脚发送。 该方法包括访问与该地址相关联的数据的存储设备，并等待与等待周期计数相关联的预定数量的时钟周期。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时从存储器件传送数据。

公开(公告)号：US20130214820A1

公开(公告)日：2013-08-22

申请号：US13845576

申请日：2013-03-18

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Ming-Chih Hsieh

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Ming-Chih Hsieh

IPC分类号： H03K3/00

CPC分类号： H03K3/00 ,  H03K19/0002 ,  H03K19/09425

摘要： An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.

摘要翻译： 集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。 输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。 输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。 所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。

公开(公告)号：US08374007B2

公开(公告)日：2013-02-12

申请号：US12820422

申请日：2010-06-22

申请人： Chih-Ting Hu ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Wu-Chin Peng ,  Kuen-Long Chang ,  Ken-Hui Chen

发明人： Chih-Ting Hu ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Wu-Chin Peng ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC分类号： H02M7/25 ,  H02M7/00

CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M2001/0032 ,  Y02B70/16

摘要： A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.

摘要翻译： 提供电源装置和供电方法。 用于具有第一功率信号的系统中的装置包括辅助单元和电源装置。 辅助单元选择性地输出根据第一功率信号的至少一个维持信号。 电源装置输出第二电力信号，其中电源装置根据至少一个维持信号维持第二电力信号，例如处于非空闲状态，例如空闲或待机状态或其他合适的定时。

公开(公告)号：US08259521B2

公开(公告)日：2012-09-04

申请号：US12190715

申请日：2008-08-13

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

IPC分类号： G11C29/00

CPC分类号： G11C29/10 ,  G11C29/12005

摘要： A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.

摘要翻译： 提供了一种用于测试多芯片封装的方法和电路。 多芯片封装至少包括存储器芯片，并且存储器芯片包括多个存储器单元。 该方法包括对存储器单元执行正常读取操作，以检查从存储器单元读取的数据是否与存储器单元中的预置数据相同; 以及对所述存储器单元执行特殊读取操作，以检查从所述存储器单元读取的数据是否与期望值相同，其中所述期望值与存储在所述存储器单元中的数据无关。