公开(公告)号：US20190312170A1

公开(公告)日：2019-10-10

申请号：US16222542

申请日：2018-12-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY

IPC: H01L31/113 ,  H01L27/146 ,  H01L31/0224

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

公开(公告)号：US10418486B2

公开(公告)日：2019-09-17

申请号：US15976452

申请日：2018-05-10

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Francois Andrieu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L27/092 ,  H01L21/762 ,  H01L29/786

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.

公开(公告)号：US10403682B2

公开(公告)日：2019-09-03

申请号：US15968474

申请日：2018-05-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Morin ,  Philippe Brun ,  Laurent-Luc Chapelon

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

Abstract: A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.

公开(公告)号：US10397503B2

公开(公告)日：2019-08-27

申请号：US15376792

申请日：2016-12-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Emmanuel Marie Malinge ,  Frederic Lalanne

IPC: H04N5/359 ,  H04N5/355 ,  H04N5/3745

Abstract: A photodiode produces photogenerated charges in response to exposure to light. An integration period collects the photogenerated charges. Collected photogenerated charges in excess of an overflow threshold are passed to an overflow sense node. Remaining collected photogenerated charges are passed to a sense node. A first signal representing the overflow photogenerated charges is read from the overflow sense node. A second signal representing the remaining photogenerated charges is read from the sense node.

公开(公告)号：US10393965B2

公开(公告)日：2019-08-27

申请号：US16148535

申请日：2018-10-01

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Nicolas Michit ,  Patrick Le Maitre

IPC: G02B6/293 ,  H04Q11/00

Abstract: A photonic interconnection elementary switch is integrated in an optoelectronic chip/The switch includes first and second linear optical waveguides which intersect to form a first intersection. Two first photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. Two second photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. A third linear optical waveguide is coupled to one of the first ring resonators and one of the second ring resonators. A fourth linear optical waveguide is coupled to another of the first resonators and to another of the second ring resonators. A base switch, complex switch, and photonic interconnection network integrated in an optoelectronic chip, include at least two of the photonic interconnection elementary switches.

公开(公告)号：US10381394B2

公开(公告)日：2019-08-13

申请号：US15813414

申请日：2017-11-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Hotellier

IPC: H01L27/146 ,  H01L31/18 ,  H01L21/768

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

公开(公告)号：US20190229147A1

公开(公告)日：2019-07-25

申请号：US16251595

申请日：2019-01-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Yannick SANCHEZ ,  Emilie DELOFFRE

IPC: H01L27/146

Abstract: An image sensor manufacturing method includes forming a cavity in a first plate and mounting an active layer including both image sensing components and logic components to the first plate. The active layer is pressed against the first plate in a manner such that the image sensing components in the active layer are located on walls of the cavity and the logic components in the active layer are located outside of the cavity.

公开(公告)号：US10361238B2

公开(公告)日：2019-07-23

申请号：US15703246

申请日：2017-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

公开(公告)号：US10332808B2

公开(公告)日：2019-06-25

申请号：US15897003

申请日：2018-02-14

Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Emmanuel Richard ,  Olivier Weber

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/12 ,  H01L27/092

Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.

公开(公告)号：US10284798B2

公开(公告)日：2019-05-07

申请号：US15730539

申请日：2017-10-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Herault ,  Pierre Malinge

IPC: H04N5/365 ,  H04N5/353 ,  H04N5/374 ,  H04N5/355 ,  H04N5/3745 ,  H04N5/235

Abstract: An image sensor includes a plurality of pixels each including a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor, the first capacitive node being linked to the readout node by a third transistor, and the readout node being linked to a node for applying a reset potential by a fourth transistor.