公开(公告)号：US07124161B2

公开(公告)日：2006-10-17

申请号：US11264778

申请日：2005-10-31

申请人： Chang Choo ,  Asher Hazanchuk

发明人： Chang Choo ,  Asher Hazanchuk

IPC分类号： G06F7/38 ,  G06F7/52

CPC分类号： G06F1/03 ,  G06F2101/12 ,  G06F2101/16 ,  H03K19/1733

摘要： Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.

公开(公告)号：US06980030B1

公开(公告)日：2005-12-27

申请号：US10606610

申请日：2003-06-26

申请人： Frank C. Wirtz, II ,  John R. Hubbard ,  Jeffrey H. Seltzer ,  Schuyler E. Shimanek

发明人： Frank C. Wirtz, II ,  John R. Hubbard ,  Jeffrey H. Seltzer ,  Schuyler E. Shimanek

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1733

摘要： Integrated circuits are disclosed that have interconnected programmable logic, and configuration memory. The interconnected programmable logic is connected by a logical interconnection network. The integrated circuits have a configurable function unit including a function unit component, such as a counter or shift register. The integrated circuits further include a configurable decoder, which decodes a value presented by the function unit component based on decoder configuration data. The integrated circuits also have at least one decoder output, which provides information about a comparison of the decoder configuration data with the value presented by the function unit component.

摘要翻译： 公开了具有互连的可编程逻辑和配置存储器的集成电路。 互连的可编程逻辑通过逻辑互连网络连接。 集成电路具有包括诸如计数器或移位寄存器的功能单元组件的可配置功能单元。 集成电路还包括可配置解码器，其基于解码器配置数据解码由功能单元组件呈现的值。 集成电路还具有至少一个解码器输出，其提供关于解码器配置数据与由功能单元组件呈现的值的比较的信息。

公开(公告)号：US20050121789A1

公开(公告)日：2005-06-09

申请号：US10727170

申请日：2003-12-04

申请人： Raminda Madurawe

发明人： Raminda Madurawe

IPC分类号： H01L23/48 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118

CPC分类号： H03K19/1735 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/11803 ,  H01L27/11898 ,  H01L27/1203 ,  H01L2924/0002 ,  H03K19/1733 ,  H03K19/17728 ,  H03K19/1776 ,  H01L2924/00

摘要： A programmable wire structure for an integrated circuit, comprising: a programmable switch coupling two nodes, said switch having a first state that connects said two nodes, and said switch having a second state that disconnects said two nodes; and a configuration circuit coupled to said programmable switch, said circuit comprising a means to program said switch between said first and second state; and a first metal layer fabricated above a silicon substrate layer, said switch and said configuration circuit fabricated substantially above said first metal layer. A semiconductor device for integrated circuits with two selectable manufacturing configurations, comprising: a first module layer having an array of structured cells, said module layer having at least one layer of metal; and a second module layer formed substantially above said first module layer comprising two selectable configurations, wherein: in a first selectable configuration a programmable interconnect structure is formed to connect said structured cells, and in a second selectable configuration a customized interconnect structure is formed to connect said structured cells.

摘要翻译： 一种用于集成电路的可编程线结构，包括：耦合两个节点的可编程开关，所述开关具有连接所述两个节点的第一状态，并且所述开关具有断开所述两个节点的第二状态; 以及耦合到所述可编程开关的配置电路，所述电路包括在所述第一和第二状态之间对所述开关进行编程的装置; 以及在硅衬底层之上制造的第一金属层，所述开关和所述配置电路基本上在所述第一金属层的上方制成。 一种用于具有两个可选制造配置的集成电路的半导体器件，包括：具有结构化单元阵列的第一模块层，所述模块层具有至少一层金属; 以及基本上在所述第一模块层上形成的包括两个可选配置的第二模块层，其中：在第一可选配置中，形成可编程互连结构以连接所述结构化单元，并且在第二可选配置中，形成定制互连结构以连接 所述结构化细胞。

公开(公告)号：US06724220B1

公开(公告)日：2004-04-20

申请号：US09924734

申请日：2001-08-07

申请人： Warren Snyder ,  Monte Mar

发明人： Warren Snyder ,  Monte Mar

IPC分类号： H03K19177

CPC分类号： H03K19/08 ,  G06F1/08 ,  G06F1/32 ,  G06F15/7867 ,  G06G7/06 ,  H03B5/364 ,  H03K3/012 ,  H03K3/014 ,  H03K3/02315 ,  H03K19/173 ,  H03K19/1733 ,  H03K19/177 ,  H03K19/17736 ,  H03K19/17748

摘要： A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The programmable array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the programmable blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input/output data between all analog and digital blocks.

摘要翻译： 具有混合模拟/数字架构的微控制器，包括具有可编程互连结构的通信阵列中的多个数字可编程块和多个模拟可编程块。 单芯片设计通过集成可以相互通信的可编程数字和模拟电路块来实现。 闪存可编程的强大的模拟和数字模块可用于实现复杂的设计应用，否则将需要多个芯片和/或单独应用。 可编程芯片架构包括具有可编程数字块的新型阵列，其可以使用可编程互连结构与可编程模拟块通信。 可编程模拟阵列包含连续时间（CT）块的补码和可以一起通信的开关电容（SC）块的补充。 模拟模块由可编程为一个或多个不同模拟功能的多功能电路组成，固定功能电路可编程，具有可变参数的固定功能。 数字模块包括标准多功能电路和具有不包括在标准数字电路中的功能的增强电路。 可编程阵列由闪存编程，编程允许动态重新配置。 也就是说，允许可编程块的“即时”重新配置。 具有连续时间模拟模块和开关电容模拟模块的可编程模拟阵列与可编程数字模块一起提供在单个芯片上。 可编程互连结构提供了所有模拟和数字模块之间的输入/输出数据的通信。

公开(公告)号：US6028463A

公开(公告)日：2000-02-22

申请号：US949992

申请日：1997-10-15

申请人： Lucian R. Albu ,  Barry K. Britton ,  Wai-Bor Leung ,  Richard G. Stuby, Jr. ,  James A. Thompson ,  Zeljko Zilic

发明人： Lucian R. Albu ,  Barry K. Britton ,  Wai-Bor Leung ,  Richard G. Stuby, Jr. ,  James A. Thompson ,  Zeljko Zilic

IPC分类号： G06F1/06 ,  G06F1/08 ,  H03K19/173 ,  H03K19/177 ,  H03L7/081 ,  H03L7/089 ,  H03K7/38

CPC分类号： H03K19/1774 ,  G06F1/06 ,  G06F1/08 ,  H03K19/1733 ,  H03K19/17704 ,  H03L7/0812 ,  H03L7/0891

摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.

摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有可编程时钟管理器（PCM），其将输入时钟转换成具有不同时钟速率的至少两个不同的输出时钟。 不同的输出时钟可用于控制FPGA内部或外部的不同进程。 例如，一个输出时钟可用于控制FPGA的输入/输出寄存器，而第二个更快的输出时钟可用于控制FPGA的内部寄存器。

公开(公告)号：US5896047A

公开(公告)日：1999-04-20

申请号：US795219

申请日：1997-02-05

申请人： Shi-dong Zhou

发明人： Shi-dong Zhou

IPC分类号： H03K5/151 ,  H03K19/003 ,  H03K19/173 ,  H03K19/094

CPC分类号： H03K19/1733 ,  H03K19/00323 ,  H03K5/151

摘要： A balanced truth-and-complement circuit. A driver circuit which generates a signal and its complement in response to an input signal; a switching circuit selects between the signal and its complement in response to external control signals; and a sense amplifier detects and amplifies the signal selected by the switching circuit. The driver circuit has NMOS transistors and inverters arranged so as to connect either the signal or its complement to the switching circuit.

摘要翻译： 一个平衡的真实和补充电路。 驱动电路，其响应于输入信号产生信号及其补码; 开关电路响应于外部控制信号在信号和其补码之间进行选择; 并且读出放大器检测和放大由开关电路选择的信号。 驱动器电路具有NMOS晶体管和反相器，其布置成将信号或其补码连接到开关电路。

公开(公告)号：US4933575B1

公开(公告)日：1992-07-21

申请号：US31044389

申请日：1989-02-14

申请人： NIPPON ELECTRIC CO

发明人： AKIRA ASO

IPC分类号： H03K3/037 ,  H03K19/173 ,  H04Q1/00 ,  H03K3/01 ,  H03K17/693 ,  H03K19/096

CPC分类号： H03K19/1733 ,  H03K3/037

公开(公告)号：US5027315A

公开(公告)日：1991-06-25

申请号：US401528

申请日：1989-08-30

申请人： Om P. Agrawal ,  Joseph A. Brcich

发明人： Om P. Agrawal ,  Joseph A. Brcich

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1733 ,  H03K19/17716

摘要： The present invention provides an output logic macrocell for controlling configuration of an output for an integrated circuit wich provides a logic signal including a register responsive to a clock signal for latching the logic signal to provide a registered signal. An output selector receives both the logic signal and the registered signal and selects responsive to an output select signal, either the logic signal or the registered signal. A feedback path provides a feedback signal as data which is selected by a feedback selector responsive to a feedback select signal for selecting the logic signal or the registered signal as the feedback signal. Further, a clock signal enable circuit, responsive to a clock enable signal, enables or disables the clock signal to clock the register. Accordingly, the register, the output selector, the feedback path, and the clock enable circuit are all dynamically controllable by respective control signals.

摘要翻译： 本发明提供一种用于控制集成电路的输出配置的输出逻辑宏单元，其提供包括响应于时钟信号的寄存器的逻辑信号，用于锁存逻辑信号以提供注册信号。 输出选择器接收逻辑信号和注册信号，并且响应输出选择信号选择逻辑信号或登记信号。 反馈路径提供反馈信号作为响应于用于选择逻辑信号或注册信号作为反馈信号的反馈选择信号的反馈选择器选择的数据。 此外，响应于时钟使能信号的时钟信号使能电路启用或禁用时钟信号来对寄存器进行时钟。 因此，寄存器，输出选择器，反馈路径和时钟使能电路都可以通过相应的控制信号动态地控制。

公开(公告)号：US4935734A

公开(公告)日：1990-06-19

申请号：US905777

申请日：1986-09-10

申请人： Kenneth Austin

发明人： Kenneth Austin

IPC分类号： H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K5/02 ,  H03K17/687 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17748 ,  G06F17/5027 ,  H03K17/687 ,  H03K19/1733 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/1778 ,  H03K5/026

摘要： Configurable semiconductor integrated circuits as-made each have a plurality of logic circuits formed at discrete sites. For each logic circuit, direct selectably conducting/non-conducting connection paths extend from its output to input of a first set of other logic circuits and to its inputs from outputs of a second set of other logic circuits. All of the sets for all of the logic circuits are each different. Other direct connection paths are selectably connectable to inputs and outputs of the logic circuits. Selection can be irreversible or reversible and involves coincident signal addressing of the sites and coded configuring of the paths at that site. Reversible selection can be via field effect transistors or bipolar transistors and can be at or near normal logic signal levels and speeds. Versatile configurable input/output arrangements are described also reconfigurable data processing systems using the reversible transistor provisions.

摘要翻译： 可配置的半导体集成电路每个都具有在离散位置处形成的多个逻辑电路。 对于每个逻辑电路，直接可选地导通/不导通的连接路径从其输出延伸到第一组其他逻辑电路的输入，并从第二组其他逻辑电路的输出延伸到其输入。 所有逻辑电路的所有集合各不相同。 其他直接连接路径可选择地连接到逻辑电路的输入和输出。 选择可以是不可逆的或可逆的，并且涉及站点的重合信号寻址和该站点路径的编码配置。 可逆选择可以通过场效应晶体管或双极晶体管，并且可以处于或接近正常的逻辑信号电平和速度。 还描述了可复用的可配置输入/输出布置，这些可配置的数据处理系统使用可逆晶体管。

公开(公告)号：US4868419A

公开(公告)日：1989-09-19

申请号：US905846

申请日：1986-09-10

申请人： Kenneth Austin

发明人： Kenneth Austin

IPC分类号： G11C11/409 ,  G06F17/50 ,  G11C11/406 ,  H03K5/02 ,  H03K17/687 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1778 ,  G06F17/5027 ,  H03K17/687 ,  H03K19/1733 ,  H03K19/1736 ,  H03K19/17704 ,  H03K5/026

摘要： A gated binary signal transmission circuit in a field effect semiconductor chip comprises a single signal-pass transistor connected between a bit signal input to one of its electrodes and a bit signal output from another of its electrodes. Its control electrode is connected for temporary energizations by switching circuitry operative only at prescribed intervals, the single signal-pass transistor being operative to pass signals between such energizations of its control electrode. Conduction of the single-pass transistor between energizations will persist, though with some decay, due to inherent capacitance and the control electrode being left "floating" between energizations.

摘要翻译： 场效应半导体芯片中的门控二进制信号传输电路包括连接在输入到其电极之一的位信号和从另一个电极输出的位信号之间的单个信号传输晶体管。 其控制电极通过仅以规定间隔工作的开关电路连接用于临时通电，单个信号传输晶体管可操作以在其控制电极的这种通电之间传递信号。 在通电之间，单通晶体管的导通将持续，尽管由于固有电容而导致一些衰减，并且控制电极在通电之间“浮动”。