公开(公告)号：US20130117790A1

公开(公告)日：2013-05-09

申请号：US13344143

申请日：2012-01-05

Applicant: Abdulkerim L. Coban ,  Clayton H. Daigle ,  Alessandro Piovaccari

Inventor： Abdulkerim L. Coban ,  Clayton H. Daigle ,  Alessandro Piovaccari

IPC: H03M3/00 ,  H04N7/20 ,  H03M1/12

CPC classification number: H03M3/394 ,  H03M3/396 ,  H03M3/398 ,  H03M3/40 ,  H03M3/448 ,  H03M3/45 ,  H03M3/452 ,  H03M3/454 ,  H04N21/6112 ,  H04N21/6118 ,  H04N21/6143

Abstract: A method of configuring an analog-to-digital converter (ADC) includes configuring the ADC to operate in one of a low-pass filter mode and a band-pass filter mode according to a value of a control signal. In at least one embodiment, the method further includes configuring an integrator gain of the ADC and a feed-forward gain of the ADC based on selection of one of a low-intermediate frequency (LIF) mode and a zero-intermediate frequency (ZIF) mode.

Abstract translation: 配置模数转换器（ADC）的方法包括根据控制信号的值将ADC配置为以低通滤波器模式和带通滤波器模式之一工作。 在至少一个实施例中，该方法还包括基于选择低中频（LIF）模式和零中频（ZIF）之一来配置ADC的积分器增益和ADC的前馈增益， 模式。

公开(公告)号：US08379760B2

公开(公告)日：2013-02-19

申请号：US12948200

申请日：2010-11-17

Applicant: Eugene M. Petilli

Inventor： Eugene M. Petilli

IPC: H04L25/34

CPC classification number: H04B1/28 ,  H03M3/364 ,  H03M3/40 ,  H03M3/41 ,  H03M3/438 ,  H03M3/496 ,  H04B1/001 ,  H04B1/0017 ,  H04B1/0025

Abstract: Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a signal-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.

Abstract translation: 公开了用于通信系统或其他系统的混合外差发射机和接收机以及用于混合外差发射和接收的相应方法。 用于将连续时间调制信号转换为离散时间数字基带信号的外差接收器包括Σ-Δ调制器。 Σ-Δ调制器是构造和布置成以RF载波频率接收调制信号的信号-δ模数转换器，并以第一中频提供量化输出。 外差接收机还可以包括构造和布置成接收由Σ-Δ模数转换器量化并以第二混频器接收信号的数据流的数字混频器。 然后，数字混合器提供表示适合于数字信号处理的基带信号的数字信号。

公开(公告)号：US20110316729A1

公开(公告)日：2011-12-29

申请号：US13254333

申请日：2010-02-24

Applicant: Hao San ,  Haruo Kobayashi

Inventor： Hao San ,  Haruo Kobayashi

IPC: H03M3/02

CPC classification number: H03M3/368 ,  H03M3/40

Abstract: To provide a complex bandpass ΔΣAD modulator capable of suppressing the influence of an image component caused by a mismatch between I- and Q-channels on a signal component with low power consumption.A complex bandpass READ modulator 10 is configured by a subtraction unit 20, a complex bandpass filter 30, an addition unit 40, a noise extraction circuit unit 50, an ADC unit 60, and a DAC unit 70. The noise extraction circuit unit 50 extracts a quantized noise signal of the ADC unit 60 based on an input signal of the ADC unit 60 and an output signal of the DAC unit 70, delays the extracted quantized noise signal by one sample time, phase-rotates the delayed signal by a predetermined angle, and feeds back the rotated signal to the input side of the ADC unit 60. Thus, a complex bandpass ΔΣAD modulator capable of suppressing the influence of the image component caused by a mismatch between I- and Q-channels on the signal component with low power consumption is provided.

Abstract translation: 提供一种复杂的带通＆Dgr＆amp; AD调制器，其能够抑制由于具有低功耗的信号分量上的I通道和Q通道之间的失配引起的图像分量的影响。 复数带通读调制器10由减法单元20，复带通滤波器30，加法单元40，噪声提取电路单元50，ADC单元60和DAC单元70构成。噪声提取电路单元50提取 基于ADC单元60的输入信号和DAC单元70的输出信号的ADC单元60的量化噪声信号将所提取的量化噪声信号延迟一个采样时间，将延迟信号相位旋转预定角度 ，并将旋转的信号反馈到ADC单元60的输入侧。因此，能够抑制由I和Q通道之间的失配引起的图像分量对该影像分量的影响的复数带通＆Dgr＆amp; 提供低功耗的信号分量。

公开(公告)号：US07852247B2

公开(公告)日：2010-12-14

申请号：US11863999

申请日：2007-09-28

Applicant: Khurram Muhammad ,  Yongtao Wang ,  Imtinan Elahi

Inventor： Khurram Muhammad ,  Yongtao Wang ,  Imtinan Elahi

IPC: H03M3/00

CPC classification number: H03M3/344 ,  H03M3/40 ,  H03M3/454 ,  H03M3/456

Abstract: One embodiment of the invention includes a mixed-signal filter. The mixed-signal filter comprises an analog signal path configured to process a first analog signal and an analog-to-digital converter (ADC) configured to convert the processed first analog signal to a digital signal. The mixed-signal filter also comprises a programmable digital feedback filter configured to filter the digital signal and a digital-to-analog converter (DAC) configured to convert the filtered digital signal to a second analog signal. The mixed-signal filter further comprises a signal combiner configured to combine an analog input signal of the mixed-signal filter and the second analog signal to generate the first analog signal.

Abstract translation: 本发明的一个实施例包括混合信号滤波器。 混合信号滤波器包括被配置为处理第一模拟信号的模拟信号路径和被配置为将经处理的第一模拟信号转换为数字信号的模拟 - 数字转换器（ADC）。 混合信号滤波器还包括被配置为对数字信号进行滤波的可编程数字反馈滤波器和被配置为将经滤波的数字信号转换为第二模拟信号的数模转换器（DAC）。 混合信号滤波器还包括信号组合器，其被配置为组合混合信号滤波器的模拟输入信号和第二模拟信号以产生第一模拟信号。

公开(公告)号：US07633422B2

公开(公告)日：2009-12-15

申请号：US12120659

申请日：2008-05-15

Applicant: Werner Blatz ,  Robert Dvorszky ,  Ulrich Grosskinsky ,  Lourans Samid ,  Marco Schwarzmueller

Inventor： Werner Blatz ,  Robert Dvorszky ,  Ulrich Grosskinsky ,  Lourans Samid ,  Marco Schwarzmueller

IPC: H03M1/34

CPC classification number: H03M3/322 ,  H03M3/40 ,  H03M3/41

Abstract: A transducer device for converting an analog DC voltage signal into a digital signal is provided, with an oscillator device for outputting a first oscillator signal and a second oscillator signal, whereby the oscillator device is formed to generate the first oscillator signal and the second oscillator signal phase-locked to one another and with the substantially same frequency from a reference signal, with an analog frequency converter connected to the oscillator device for transforming the analog DC voltage signal by the first oscillator signal in a first spectral range with a first center frequency to obtain a transformed signal, with an analog-to-digital converter for converting the transformed signal into a transformed digital signal; and with a digital frequency converter connected to the oscillator device for transforming the transformed digital signal by means of the second oscillator signal in a second spectral range with a second center frequency to obtain the digital signal.

Abstract translation: 提供了一种用于将模拟直流电压信号转换为数字信号的换能器装置，具有用于输出第一振荡器信号和第二振荡器信号的振荡器装置，由此形成振荡器装置以产生第一振荡器信号和第二振荡器信号 相互锁定并且具有与参考信号基本上相同的频率，其中模拟频率转换器连接到振荡器装置，用于在第一频谱范围内利用第一中心频率将第一振荡器信号的模拟直流电压信号变换为 使用用于将经变换的信号转换成变换的数字信号的模数转换器获得变换的信号; 以及连接到所述振荡器装置的数字频率转换器，用于通过具有第二中心频率的第二频谱范围内的所述第二振荡器信号变换所述经变换的数字信号，以获得所述数字信号。

公开(公告)号：US07443324B1

公开(公告)日：2008-10-28

申请号：US11807572

申请日：2007-05-29

Applicant: Khurram Muhammad

Inventor： Khurram Muhammad

IPC: H03M1/20 ,  H03M3/00

CPC classification number: H03M3/332 ,  H03M3/328 ,  H03M3/40

Abstract: A signal processor includes a sigma-delta modulator. The input signal to the signal-delta modulator may contain a dc component that generates spurious tones in the modulator output. An input signal to the signal processor is multiplied by an output of a waveform generator to produce an up-converted signal prior to processing by the sigma-delta modulator. Preferably, the waveform generator produces a random signal, which may be a pseudorandom signal. However, other waveforms such as a bipolar binary waveform can also be used. The output of the waveform generator is delayed and multiplied by the output of the sigma-delta modulator to produce a down-converted signal with reduced spurious tones. The delay matches the delay of the sigma-delta modulator. The down-converted signal is filtered with a low-pass filter.

Abstract translation: 信号处理器包括Σ-Δ调制器。 到信号-Δ调制器的输入信号可以包含在调制器输出中产生杂散音调的直流分量。 信号处理器的输入信号乘以波形发生器的输出，以在由Σ-Δ调制器处理之前产生上变频信号。 优选地，波形发生器产生随机信号，其可以是伪随机信号。 然而，也可以使用诸如双极二进制波形的其它波形。 波形发生器的输出被延迟并与Σ-Δ调制器的输出相乘，以产生具有降低的伪噪声的下变频信号。 延迟匹配Σ-Δ调制器的延迟。 下变频信号用低通滤波器滤波。

公开(公告)号：US20060284751A1

公开(公告)日：2006-12-21

申请号：US11408941

申请日：2006-04-24

Applicant: Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Akira Hayakawa ,  Hiroyuki Hagiwara ,  Yoshitaka Jingu ,  Kazuyuki Kobayashi ,  Toshiro Tsukada

Inventor： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Akira Hayakawa ,  Hiroyuki Hagiwara ,  Yoshitaka Jingu ,  Kazuyuki Kobayashi ,  Toshiro Tsukada

IPC: H03M3/00

CPC classification number: H03M3/34 ,  H03M3/40 ,  H03M3/402 ,  H03M3/424 ,  H03M3/454

Abstract: In a first-order complex band-pass filter, multiplexers are alternately switched over between time intervals of phases A and B, where the multiplexers includes two multiplexers provided at input and output stages, and a multiplexer provided in a feedback circuit of each of first-order filters and being switching over whether to invert a sign of a feedback signal. Then in a circuit part sandwiched between the multiplexers, a processing performed by an I circuit part and a processing performed by a Q circuit part are alternately switched over so that a sign of a signal inputted to an adder is inverted.

Abstract translation: 在一阶复数带通滤波器中，多路复用器在相位A和B的时间间隔之间交替切换，其中多路复用器包括在输入和输出级提供的两个多路复用器，以及多路复用器，其设置在第一 - 顺序滤波器并切换是否反转反馈信号的符号。 然后在夹在多路复用器之间的电路部分中，交替地切换由I电路部分执行的处理和由Q电路部分执行的处理，使得输入到加法器的信号的符号反转。

公开(公告)号：US20060115005A1

公开(公告)日：2006-06-01

申请号：US10998212

申请日：2004-11-26

Applicant: Ronald Hickling

Inventor： Ronald Hickling

IPC: H04B14/06 ,  H04L27/20

CPC classification number: H03C3/40 ,  H03M3/40 ,  H03M3/50 ,  H04B1/69 ,  H04B14/062

Abstract: A flexible and programmable circuit for generating a radio frequency signal for transmission includes two delta-sigma modulators, a quadrature clock generator for generating two clock signals having a 90 degree phase difference, two commutators for multiplying the two modulator outputs by +1 and −1 on alternating half cycles of the two quadrature clock signals respectively, a summer for summing the two commutated outputs, and a filter for removing unwanted frequency components before transmission. The circuit directly generates a radio frequency signal without the need for additional frequency translation after the commutation stage.

Abstract translation: 用于产生用于传输的射频信号的灵活且可编程的电路包括两个Δ-Σ调制器，用于产生具有90度相位差的两个时钟信号的正交时钟发生器，两个用于将两个调制器输出乘以+1和-1的换向器 在两个正交时钟信号的交替半周期上，分别用于对两个换向输出求和的加法器和用于在发送之前去除不需要的频率分量的滤波器。 电路直接产生射频信号，而不需要在换向级之后进行额外的频率转换。

公开(公告)号：US20050285766A1

公开(公告)日：2005-12-29

申请号：US11157848

申请日：2005-06-22

Applicant: Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Atsushi Wada

Inventor： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Atsushi Wada

IPC: H03M1/06 ,  H03M3/00 ,  H03M3/04

CPC classification number: H03M3/34 ,  H03M1/0665 ,  H03M3/40 ,  H03M3/424 ,  H03M3/464

Abstract: A complex band-pass ΔΣ AD modulator is provided with a subtracter device, a complex band-pass filter, first and second AD converters, and first and second DA converters. The first and second DA converters and first and second logic circuits are sandwiched by first and second multiplexers. At a first timing of a clock signal, the first multiplexer inputs and outputs the first and second digital signals as they are, and at a second timing thereof, the first multiplexer inputs the first and second digital signals, and outputs the first digital signal as a second digital signal and outputs the second digital signal as a first digital signal. The second multiplexer inputs and outputs first and second analog signals similarly. The first and second logic circuits substantially noise-shapes non-linearities of the first and second DA converters by realizing complex digital and analog filters, using high-pass and low-pass element rotation methods.

Abstract translation: 复数带通DeltaSigma AD调制器具有减法器件，复带通滤波器，第一和第二AD转换器以及第一和第二DA转换器。 第一和第二DA转换器和第一和第二逻辑电路夹在第一和第二多路复用器之间。 在时钟信号的第一定时，第一多路复用器原样输入并输出第一和第二数字信号，并且在其第二定时，第一多路复用器输入第一和第二数字信号，并将第一数字信号作为 第二数字信号并输出​​第二数字信号作为第一数字信号。 第二多路复用器类似地输入和输出第一和第二模拟信号。 通过使用高通和低通元素旋转方法实现复杂的数字和模拟滤波器，第一和第二逻辑电路基本上噪声地形成第一和第二DA转换器的非线性。

公开(公告)号：US06903672B1

公开(公告)日：2005-06-07

申请号：US10448694

申请日：2003-05-30

Applicant: Roberto Sergio Matteo Maurino

Inventor： Roberto Sergio Matteo Maurino

IPC: H03M3/00

CPC classification number: H03M3/34 ,  H03M3/40

Abstract: A signal processing component is provided where a swapper 702 is provided upstream of real and imaginary processing elements 704 and 706 within a system for processing complex signals. A further swapper 710 is provided downstream of the elements 704 and 706. The swappers 702 and 710 operate in unison.

Abstract translation: 提供信号处理部件，其中在用于处理复杂信号的系统内的实际和虚拟处理元件704和706的上游提供交换器702。 在元件704和706的下游提供另外的交换器710。 切换器702和710一致地操作。