公开(公告)号：US20050036502A1

公开(公告)日：2005-02-17

申请号：US10895159

申请日：2004-07-20

Applicant: Alain Blanc ,  Rene Glaise ,  Francois Maut ,  Michel Poret

Inventor： Alain Blanc ,  Rene Glaise ,  Francois Maut ,  Michel Poret

IPC: H04L12/43 ,  H04L12/56

CPC classification number: H04L49/9036 ,  H04L49/201 ,  H04L49/3036 ,  H04L49/3045 ,  H04L49/90

Abstract: A system and a method to avoid packet traffic congestion in a shared memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers and handling unicast as well as multicast traffic. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of data packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the memory shared switch core only if the switch core can send it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.

Abstract translation: 一种避免共享存储交换机核心中的数据包流量拥塞的系统和方法，同时显着减少交换机核心和相关联的出口缓冲区中的共享存储器的数量以及处理单播以及组播流量。 根据本发明，分组交换结构的所有入口适配器的虚拟输出排队（VOQ）被折叠到其中央交换机核心中以允许有效的流控制。 数据包从入口缓冲区传输到交换机核心受到请求/确认机制的约束。 因此，只有当交换机核心才能将其发送到对应的出口缓冲区时，才将数据包从虚拟输出队列发送到存储器共享交换机内核。 基于令牌的机制允许交换机核心确定出口缓冲区的占用水平。 因此，由于交换机核心知道输入和输出适配器的状态，因此能够优化分组交换并避免分组拥塞。 此外，由于分组只有在可以发送到对应的出口缓冲器的情况下才允许在交换机核心中，所以共享存储器被减少。

公开(公告)号：US20040196855A1

公开(公告)日：2004-10-07

申请号：US10407814

申请日：2003-04-03

Applicant: U4EA Technologies Limited

Inventor： Neil James Davies ,  Judith Yvonne Holyer ,  Laura Anne Lafave ,  Peter William Thompson ,  Christopher James Vowden ,  Graham Willmott

IPC: H04L012/28

CPC classification number: H04L49/90 ,  H04L47/10 ,  H04L47/20 ,  H04L47/22 ,  H04L47/2433 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/54 ,  H04L47/56 ,  H04L47/6215 ,  H04L49/9036 ,  H04L2012/5647 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/568 ,  H04Q11/0478

Abstract: There is disclosed a method and controller for controlling an information flow in an acyclic data transmission system including receiving a plurality of data packets, and allocating a priority level for each data packet including a class of loss for the data packet and a class of urgency of service for the data packet. The method and controller also include servicing the data packets in accordance with the priority levels and outputting the data packets at a configured rate.

Abstract translation: 公开了一种用于控制非循环数据传输系统中的信息流的方法和控制器，包括接收多个数据分组，并为每个数据分组分配包括数据分组丢失类别的优先级， 为数据包提供服务。 方法和控制器还包括根据优先级对数据分组进行服务，并以配置的速率输出数据分组。

公开(公告)号：US06788697B1

公开(公告)日：2004-09-07

申请号：US09635898

申请日：2000-08-11

Applicant: James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

IPC: H04L1226

CPC classification number: H04L49/9036 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9026 ,  H04L49/9052 ,  H04L49/9078

Abstract: An improved buffer management process is disclosed wherein the buffer is shared among a plurality of packet queues. The improved buffer management process comprises computing a common queue threshold value based upon the aggregate size of the plurality of packet queues and a predetermined buffer threshold value. The common queue threshold value is then used to manage the size of each of the plurality of packet queues and thereby manage the buffer.

Abstract translation: 公开了一种改进的缓冲器管理过程，其中缓冲器在多个分组队列之间共享。 改进的缓冲器管理过程包括基于多个分组队列的聚合大小和预定的缓冲器阈值来计算公共队列阈值。 然后使用公共队列阈值来管理多个分组队列中的每一个的大小，从而管理缓冲器。

公开(公告)号：US20040151177A1

公开(公告)日：2004-08-05

申请号：US10761395

申请日：2004-01-20

Inventor： Tom E. Burton ,  Dominic J. Gasbarro ,  Brian M. Leitner ,  Dean S. Susnow

IPC: H04L012/56

CPC classification number: H04L49/9089 ,  H04L49/103 ,  H04L49/35 ,  H04L49/90 ,  H04L49/9036 ,  H04L49/9057 ,  H04L49/9063 ,  H04L49/9068 ,  H04L69/22

Abstract: A device to create, receive, and transmit packets of data in a packet switching network. This device employs a direct memory access packet controller which would interface between memory contained within a computer system and a packet switched network. This direct memory access packet controller would utilize one or more micro-engines that would dynamically allocate buffer space to process received packets of data. This direct memory access packet controller would further utilize a transmit cell FIFO circuit to allocate buffer space to packets being transmitted. In addition, a sequencer would act to control the workflow of packets being received and transmitted.

公开(公告)号：US06768738B1

公开(公告)日：2004-07-27

申请号：US09393326

申请日：1999-09-10

Applicant: Takeki Yazaki ,  Takeshi Aimoto ,  Kazuo Sugai ,  Nobuhito Matsuyama

Inventor： Takeki Yazaki ,  Takeshi Aimoto ,  Kazuo Sugai ,  Nobuhito Matsuyama

IPC: H04L1256

CPC classification number: H04L12/46 ,  H04L29/06 ,  H04L45/00 ,  H04L45/54 ,  H04L45/60 ,  H04L45/745 ,  H04L47/50 ,  H04L47/6215 ,  H04L49/205 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9036 ,  H04L67/327 ,  H04L69/12 ,  H04L2012/5636 ,  H04Q11/0478

Abstract: A packet forwarding apparatus provided with a plurality of line interface units, comprises a routing processing unit for referring to a routing table, based on header information of received packet to specify one of output lines to output the received packet, a flow detection unit for referring to an entry table, in which a plurality of entries with flow conditions and control information are registered, to retrieve control information defined by the entry with a flow condition which coincides with that of the header information of the received packet, and a packet forwarding unit for transferring the received packet to one of the line interface units connected to the output line specified by the routing processing unit. The entry table id divided into a plurality of subtables corresponding to the values of flow attributes associated with the received packets and the flow detection unit retrieves the control information from one of said subtables specified by the value of the flow attribute corresponding to the received packet.

Abstract translation: 具有多个线路接口单元的分组转发装置包括：路由处理单元，用于根据接收到的分组的头信息来参考路由表，以指定输出所述接收分组的输出行之一;流量检测单元，用于参考 将具有流量条件和控制信息的多个条目登记到条目表中，以检索由条目定义的控制信息，其中流程条件与接收到的分组的标题信息的流条件一致;以及分组转发单元 用于将接收到的分组传送到连接到由路由处理单元指定的输出线的线路接口单元之一。 入口表id被划分为与接收到的分组相关联的流属性的值对应的多个子表，并且流检测单元从与接收到的分组对应的流属性的值指定的所述子表之一中检索控制信息。

公开(公告)号：US06675222B1

公开(公告)日：2004-01-06

申请号：US10270796

申请日：2002-10-11

Applicant: Brian A. Petersen ,  James R. Rivers

Inventor： Brian A. Petersen ,  James R. Rivers

IPC: G06F1516

CPC classification number: H04L12/44 ,  H04L12/5601 ,  H04L29/06 ,  H04L47/13 ,  H04L47/2433 ,  H04L47/30 ,  H04L47/32 ,  H04L49/103 ,  H04L49/108 ,  H04L49/3072 ,  H04L49/309 ,  H04L49/90 ,  H04L49/9036 ,  H04L2012/5651 ,  H04L2012/5667

Abstract: Methods and apparatus for providing a network data switch and buffer system are disclosed. In a switch having a memory associated therewith, the memory including a general memory and a plurality of dedicated memory segments, the general memory being available to a plurality of users associated with one or more network devices and each one of the plurality of dedicated memory segments being associated with one of the plurality of users, a method of storing data includes receiving data from a source network device connected to the switch. The data is then stored in a data buffer so that a portion of one of the plurality of dedicated memory segments is allocated when the general memory has been depleted.

Abstract translation: 公开了提供网络数据交换和缓冲系统的方法和装置。 在具有与其相关联的存储器的开关中，存储器包括一般存储器和多个专用存储器段，一般存储器可用于与一个或多个网络设备相关联的多个用户以及多个专用存储器段中的每一个 与多个用户中的一个相关联，存储数据的方法包括从连接到交换机的源网络设备接收数据。 然后将数据存储在数据缓冲器中，使得当一般存储器已经耗尽时，分配多个专用存储器段中的一个专用存储器段的一部分。

公开(公告)号：US20030081624A1

公开(公告)日：2003-05-01

申请号：US10281340

申请日：2002-10-24

Inventor： Vijay Aggarwal ,  Wayne Boland ,  Brittain McKinley ,  Alan Beardsley ,  John Flanders

IPC: H04L012/28 ,  H04L012/56

CPC classification number: H04L49/3027 ,  H04L12/5601 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/6215 ,  H04L49/101 ,  H04L49/205 ,  H04L49/25 ,  H04L49/254 ,  H04L49/30 ,  H04L49/3018 ,  H04L49/3081 ,  H04L49/505 ,  H04L49/90 ,  H04L49/9036 ,  H04L2012/5651 ,  H04L2012/5658 ,  H04L2012/5665 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04Q11/0478

Abstract: The present invention provides systems for improved quality of service and traffic management in network routers and other devices. This is achieved, according to one aspect of the invention, by coupling a plurality of queue processors to a plurality of input interfaces that receive data from one or more respective network connections. Each queue processor, in coordination with an associated scheduler that schedules dequeing of data from one or more queues, maintains the quality of service levels with respect to throughput, and delivers the data for a particular output context based on priority to a respective output interface. The output interface is coupled to the plurality of queue processors and transfers the data to one or more respective network connections. In addition, a plurality of output interfaces can be coupled to respective pluralities of queue processors for transferring data therefrom to one or more destination network connections. Packets, cell, datagrams and so forth passing through the router are disassembled and marked with one or more priority levels. Prior to exiting the router they re reassembled (based on those priorities, inter alia) into their constituent forms for continued routing on the network.

Abstract translation: 本发明提供了用于改善网络路由器和其他设备中的服务质量和流量管理的系统。 根据本发明的一个方面，通过将多个队列处理器耦合到从一个或多个相应网络连接接收数据的多个输入接口来实现。 每个队列处理器与调度来自一个或多个队列的数据的相关联的调度器协调，维持关于吞吐量的服务质量水平，并且基于优先级将特定输出上下文的数据传送到相应的输出接口。 输出接口耦合到多个队列处理器并将数据传送到一个或多个相应的网络连接。 此外，多个输出接口可以耦合到相应的多个队列处理器，用于将数据从其传送到一个或多个目的地网络连接。 通过路由器的数据包，单元，数据报等被拆卸并标有一个或多个优先级。 在退出路由器之前，他们重新组装（基于这些优先级，特别是）到其组成形式，以在网络上继续路由。

公开(公告)号：US20030056001A1

公开(公告)日：2003-03-20

申请号：US09909739

申请日：2001-07-20

Inventor： Ashutosh Mate ,  Atul Mahamuni ,  Vijay Chander

IPC: G06F015/173

CPC classification number: H04L47/6215 ,  H04L12/5601 ,  H04L45/00 ,  H04L45/50 ,  H04L45/54 ,  H04L45/7457 ,  H04L47/10 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/627 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9036 ,  H04L49/9047 ,  H04L49/9073

Abstract: The present invention relates to a method and system for supporting in a router a plurality of data flows using a ternary content addressable memory (TCAM) in which the number of accesses to write to the TCAM is optimized to improve efficiency of updating and subsequent look up. To accommodate the plurality of data flows, the TCAM is partitioned into at least two partitions in which a first portion includes indices having a higher priority and a second portion includes indices having a lower priority. For example, multiple protocol label switching (MPLS) flows and IP-Virtual Private Network (VPN) can be added to the first partition and policy based routing flows can be added to the second partition. During subsequent TCAM look-up of a prefix of an incoming packet the MPLS or IP-VPN flow will subsume any matching policy based routing flow, such as flows classified by an access control list or traffic manager flows.

Abstract translation: 本发明涉及一种使用三进制内容可寻址存储器（TCAM）在路由器中支持多个数据流的方法和系统，其中对TCAM写入的访问次数被优化以提高更新和后续查找的效率 。 为了适应多个数据流，TCAM被划分为至少两个分区，其中第一部分包括具有较高优先级的索引，第二部分包括具有较低优先级的索引。 例如，可以将多协议标签交换（MPLS）流和IP虚拟专用网（VPN）添加到第一分区，并且可以将基于策略的路由流添加到第二分区。 在随后的TCAM查询中，进入分组的前缀，MPLS或IP-VPN流将包含任何基于匹配策略的路由流，例如由访问控制列表或流量管理器流分类的流。

公开(公告)号：US20030043840A1

公开(公告)日：2003-03-06

申请号：US10078944

申请日：2002-02-19

Inventor： Yasushi Kurokawa ,  Hideyo Fukunaga ,  Takashi Maemoto ,  Yuuki Okumura

IPC: H04L012/413

CPC classification number: H04L49/901 ,  H04L45/16 ,  H04L47/15 ,  H04L47/2441 ,  H04L47/50 ,  H04L49/9036

Abstract: The present invention is directed to the provision of a packet transmission apparatus and, more particularly, to a packet transmission apparatus achieving high-speed processing capability and enhanced relay quality for multicast packets. The packet transmission apparatus comprises: a non-copy packet arbiter which selects one of the non-copy packets by a prescribed algorithm, and requests transmission of the selected non-copy packet; a copy packet arbiter which selects one of the copy packets by a prescribed algorithm, and requests transmission of the selected copy packet; and a final arbiter which selects either one of the transmit requests, the transmit request from the non-copy packet arbiter or the transmit request from the copy packet arbiter, by a prescribed algorithm, and requests transmission of the selected packet, and wherein: the packet transmission apparatus transmits the packet requested by the final arbiter for transmission.

Abstract translation: 本发明旨在提供一种分组发送装置，更具体地说，涉及一种实现多播分组的高速处理能力和增强的中继品质的分组发送装置。 分组发送装置包括：非复制分组仲裁器，其通过规定的算法选择非复制分组之一，并请求传输所选择的非复制分组; 复制分组仲裁器，其通过规定的算法选择一个复制分组，并请求传输所选择的复制分组; 以及最终仲裁器，其通过规定的算法选择发送请求中的一个，来自非复制分组仲裁器的发送请求或来自复制分组仲裁器的发送请求，并请求传输所选择的分组，并且其中： 分组发送装置发送由最终仲裁器请求的分组进行传输。

公开(公告)号：US20020087708A1

公开(公告)日：2002-07-04

申请号：US09741829

申请日：2000-12-22

Inventor： Arthur John Low ,  Stephen J. Davis

IPC: G06F015/16 ,  G06F005/00 ,  G06F003/06 ,  G06F003/05 ,  G06F003/023 ,  G06F003/00 ,  G06F003/02 ,  G06F015/173

CPC classification number: H04L67/42 ,  H04L49/90 ,  H04L49/9036 ,  H04L63/0428 ,  H04L63/0485 ,  H04L67/34 ,  H04L69/22 ,  H04L69/329

Abstract: A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list processes to perform on the packet of data and am ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is not next process for a packet at which time it is provided to an output port.

Abstract translation: 公开了一种用于处理数据的数据处理器和方法。 处理器具有用于接收待处理数据的数据包的输入端口。 主控制器用于分析数据包，并提供一个报头，其中包括对数据包执行的列表进程和序列。 主控制器被编程有与处理器的整体处理功能相关的过程相关数据。 标题附加到数据包。 具有附加标题信息的分组被存储在缓冲器中。 缓冲器控制器用于基于分组内的报头来确定存储在缓冲器内的每个分组，以处理分组的下一个处理器。 然后，控制器将该分组提供给所确定的处理器进行处理。 返回处理后的数据包，表示处理完成。 例如，可以从进程列表中删除该进程。 缓冲器控制器重复地确定下一个处理，直到在其被提供给输出端口的分组没有下一个处理。