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公开(公告)号：US20230072467A1
公开(公告)日：2023-03-09
申请号：US17939718
申请日：2022-09-07
申请人： HYPERSTONE GMBH
摘要： A method for read reference voltage calibration of a non-volatile memory, NVM, such as flash memory, particularly of the NAND type, comprises: Reading from the NVM predetermined reference data stored therein and being encoded with an error correction code, ECC, wherein the reading is performed when a read reference voltage of the NVM, which is used as a reference voltage, such as a threshold voltage, for the reading, is set at a defined voltage level; decoding the read data and observing a number of bit errors, e.g., in a codeword, of the read data in relation to the reference data; and defining a new voltage level of the read reference voltage for a subsequent reading of data from the NVM based on the observed number of bit errors and setting the read reference voltage to the defined new voltage level.
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公开(公告)号：US11600354B2
公开(公告)日：2023-03-07
申请号：US17301348
申请日：2021-03-31
摘要： Disclosed is a system including a memory device having a plurality of physical cells and a processing device, operatively coupled with the memory device, to perform operations that include selecting, responsive to detecting a power event, a subset of a plurality of memory cells of the memory device, the memory device being characterized by auxiliary read metadata identifying one or more read offsets for each of the plurality of memory cells, the one or more read offsets representing corrections to read signals applied to the respective memory cell during a read operation. The operations further include performing one or more diagnostic read operations for each of the subset of the plurality of memory cells of the memory device and modifying the auxiliary read metadata by updating the one or more read offsets for at least some of the plurality of memory cells of the memory device.
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93.发明申请公开(公告)号：US20230060621A1
公开(公告)日：2023-03-02
申请号：US17460359
申请日：2021-08-30
发明人： Katherine H. CHIANG
摘要： Various aspects include methods and devices for implementing the methods for error checking a memory system. Aspects may include receiving, from a row buffer of a memory, access data corresponding to a column address of a memory access, in which the row buffer has data of an activation unit of the memory corresponding to a row address of the memory access, determining multiple error correction codes (ECCs) for the access data using the column address, and checking the access data for an error utilizing at least one of the multiple ECCs. In some aspects, the multiple ECCs may include a first ECC having data from an access unit of the memory corresponding with the column address, and at least one second ECC having data from the access unit and data from the activation unit other than from the access unit.
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公开(公告)号：US20230056231A1
公开(公告)日：2023-02-23
申请号：US17532826
申请日：2021-11-22
申请人： SK hynix Inc.
发明人： Munseon JANG , Hoiju CHUNG , Jang Ryul KIM
摘要： A memory system includes a memory; and a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when a read operation needs to be performed in a region of the memory including the error location.
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公开(公告)号：US11587638B2
公开(公告)日：2023-02-21
申请号：US17401213
申请日：2021-08-12
摘要： A memory sub-system configured to generate or update a model for reading memory cells in a memory device. For example, in response to a processing device of a memory sub-system transmitting to a memory device read commands that are configured to instruct the memory device to retrieve data from a group of memory cells formed on an integrated circuit die in the memory device, the memory device may measure signal and noise characteristics of the group of memory cells during execution of the read commands. Based on the signal and noise characteristics the memory sub-system can generate or update, measured during the execution of the read commands a model of changes relevant to reading data from the group of memory cells. The changes can be a result of damage, charge loss, read disturb, cross-temperature effect, etc.
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公开(公告)号：US20230049201A1
公开(公告)日：2023-02-16
申请号：US17648396
申请日：2022-01-19
发明人： Deping He , Jonathan S. Parry , Chun Sum Yeung
摘要： Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.
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公开(公告)号：US20230046724A1
公开(公告)日：2023-02-16
申请号：US17979432
申请日：2022-11-02
发明人： Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Sampath K. Ratnam , Peter Feeley , Sivagnanam Parthasarathy , Devin M. Batutis , Xiangang Luo
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.
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公开(公告)号：US20230044318A1
公开(公告)日：2023-02-09
申请号：US17394232
申请日：2021-08-04
发明人： Zhenlei Shen , Tingjun Xie , Zhenming Zhou
摘要： A system includes a memory device storing groups of managed units and a processing device operatively coupled to the memory device. The processing device is to, during power on of the memory device, perform including: causing a read operation to be performed at a subset of a group of managed units; determining a bit error rate related to data read from the subset of the group of managed units; and in response to the bit error rate satisfying a threshold criterion, causing a rewrite of the data stored at the group of managed units.
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公开(公告)号：US11574700B2
公开(公告)日：2023-02-07
申请号：US17245568
申请日：2021-04-30
发明人： Jooyong Park , Minsu Kim , Daeseok Byeon , Pansuk Kwak
IPC分类号： G11C29/00 , G06F11/20 , G11C16/04 , G11C29/44 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/12 , G11C29/02 , G11C29/52 , G11C29/42 , G11C29/24
摘要： A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.
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公开(公告)号：US11574697B2
公开(公告)日：2023-02-07
申请号：US17344027
申请日：2021-06-10
申请人： SK hynix Inc.
发明人： Fan Zhang , Aman Bhatia , Haobo Wang
IPC分类号： G11C29/42 , H03K19/17728 , G11C11/408 , G11C11/4093
摘要： Devices, systems and methods for improving a decoding operation in a non-volatile memory are described. An example method includes performing a first hard read to obtain a first set of values stored in a plurality of cells, storing the first set of values in a first buffer, performing a plurality of subsequent hard reads on the plurality of cells to obtain a plurality of subsequent sets of values, performing, for each subsequent set of values, the following operations: computing a quality metric, storing, in a second buffer, a difference between the subsequent set of values and the set of values stored in the first buffer, wherein the difference is stored in a compressed format, and storing, in response to the quality metric exceeding a threshold, the subsequent set of values in the first buffer, and generating, based on the first buffer and the second buffer, the log-likelihood ratio.
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