公开(公告)号：US06218260B1

公开(公告)日：2001-04-17

申请号：US09036356

申请日：1998-03-06

申请人： Seung-Hwan Lee ,  Sang-Hyeop Lee ,  Young-Sun Kim ,  Se-Jin Shim ,  You-Chan Jin ,  Ju-Tae Moon ,  Jin-Seok Choi ,  Young-Min Kim ,  Kyung-Hoon Kim ,  Kab-Jin Nam ,  Young-Wook Park ,  Seok-Jun Won ,  Young-Dae Kim

发明人： Seung-Hwan Lee ,  Sang-Hyeop Lee ,  Young-Sun Kim ,  Se-Jin Shim ,  You-Chan Jin ,  Ju-Tae Moon ,  Jin-Seok Choi ,  Young-Min Kim ,  Kyung-Hoon Kim ,  Kab-Jin Nam ,  Young-Wook Park ,  Seok-Jun Won ,  Young-Dae Kim

IPC分类号： H01L2120

CPC分类号： H01L28/84 ,  Y10S438/964

摘要： Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer. The diffusion barrier layer is preferably made of a material of sufficient thickness to prevent reaction between the dielectric layer and the lower electrode and also prevent out-diffusion of dopants from the HSG silicon surface layer to the dielectric layer. The dielectric layer is also preferably formed of a material having high dielectric strength to increase capacitance.

摘要翻译： 形成集成电路电容器的方法包括以下步骤：通过在半导体衬底上形成导电层图案（例如，硅层）形成电容器的下电极，然后形成第一导电类型的半球形晶粒（HSG）硅表面层 导电层图案。 在导电层图案的外表面上包含HSG硅表面层增加给定横向尺寸的下电极的有效表面积。 HSG硅表面层还优选地充分掺杂有第一导电型掺杂剂（例如，N型），以使电容器反向偏置时可能在下电极中形成的任何耗尽层的尺寸最小化，从而提高电容器的特性 Cmin / Cmax比。 扩散阻挡层（例如，氮化硅）也形成在下电极上，然后在扩散阻挡层上形成电介质层。 扩散阻挡层优选由足够厚度的材料制成，以防止介电层和下电极之间的反应，并且还防止掺杂剂从HSG硅表面层向电介质层的扩散。 电介质层还优选由具有高介电强度的材料形成以增加电容。

公开(公告)号：US5763300A

公开(公告)日：1998-06-09

申请号：US709249

申请日：1996-09-10

申请人： In-sung Park ,  Kyung-hoon Kim

发明人： In-sung Park ,  Kyung-hoon Kim

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8242

CPC分类号： H01L28/40

摘要： A microelectronic capacitor is formed by nitrating the surface of a conducting electrode on a microelectronic substrate. The nitrated surface of the conductive electrode is then oxidized. The nitrating and oxidizing steps collectively form a film of silicon oxynitride on the conductive electrode. A tantalum pentoxide film is then formed on the oxidized and nitrated surface of the conductive electrode. The tantalum pentoxide film may then be thermally treated in the presence of oxygen gas. High performance microelectronic capacitors are thereby provided.

摘要翻译： 通过在微电子衬底上硝化导电电极的表面形成微电子电容器。 然后将导电电极的硝化表面氧化。 硝化和氧化步骤在导电电极上共同形成氮氧化硅膜。 然后在导电电极的氧化和硝化表面上形成五氧化二钽膜。 然后可以在氧气存在下对五氧化钽膜进行热处理。 从而提供高性能微电子电容器。

公开(公告)号：US09007291B2

公开(公告)日：2015-04-14

申请号：US13278042

申请日：2011-10-20

申请人： Seung-Kyu Lee ,  Dong-Hoon Lee ,  Chul-Ho Kim ,  Kyung-Hoon Kim ,  Se-Hyang Kim

发明人： Seung-Kyu Lee ,  Dong-Hoon Lee ,  Chul-Ho Kim ,  Kyung-Hoon Kim ,  Se-Hyang Kim

IPC分类号： G09G3/36 ,  H03K19/0185

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G2300/0876 ,  H03K19/018507

摘要： An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.

摘要翻译： 公开了一种有源电平偏移（ALS）驱动电路和包括ALS驱动电路的液晶显示装置。 所述ALS驱动电路包括被配置为向第一节点施加第一极性电压并且向第二节点施加第二极性电压的输入单元，被配置为调整所述第一节点和所述第二节点的电压的电平补偿单元，以及 输出单元，被配置为根据第一和第二节点的调整的电压交替地输出第一电源电压和第二电源电压。

公开(公告)号：US08909972B2

公开(公告)日：2014-12-09

申请号：US13219620

申请日：2011-08-27

申请人： Kyung Hoon Kim ,  Hong Bae Kim

发明人： Kyung Hoon Kim ,  Hong Bae Kim

IPC分类号： G06F1/00 ,  H03L7/06

CPC分类号： H03L7/06 ,  G11C7/222 ,  G11C2207/2272 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/10

摘要： A latency control circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a clock signal by a delay time varied according to any one of dual locking points, and generate a loop change signal according to a locking point change; a control unit configured to generate a latency control signal in response to a reset signal, a delay signal generated by delaying the reset signal by a first delay time, and the loop change signal; and a latency signal generation unit configured to adjust a latency of a command signal in response to the latency control signal and output a latency signal.

摘要翻译： 延迟控制电路包括：延迟锁定环（DLL），被配置为通过根据双锁定点中的任一个延迟时钟信号延迟时钟信号来产生DLL时钟信号，并且根据锁定点生成环路变化信号 更改; 控制单元，被配置为响应于复位信号产生等待时间控制信号，通过将复位信号延迟第一延迟时间而产生的延迟信号和环路变化信号; 以及延迟信号生成单元，被配置为响应于等待时间控制信号来调整命令信号的等待时间并输出等待时间信号。

公开(公告)号：US08872557B2

公开(公告)日：2014-10-28

申请号：US13601661

申请日：2012-08-31

申请人： Kyung Hoon Kim

发明人： Kyung Hoon Kim

IPC分类号： G11C7/22

CPC分类号： G11C7/22 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/2254

摘要： A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.

摘要翻译： 一种用于半导体装置的数据输出定时控制电路包括相位调整单元。 相位调整单元被配置为将延迟控制码的代码值的读取命令的相位与通过将外部时钟延迟大到预定延迟量而获得的多个延迟时钟分别延迟，延迟 移位读取命令与可变延迟量一样大，并将延迟结果作为输出使能标志信号输出。

公开(公告)号：US08710886B2

公开(公告)日：2014-04-29

申请号：US12005879

申请日：2007-12-28

申请人： Kyung-Hoon Kim ,  Jun-Woo Lee ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Jun-Woo Lee ,  Taek-Sang Song

IPC分类号： H03K3/017 ,  H03K5/156

CPC分类号： H03K5/1565 ,  H03K5/1534

摘要： A semiconductor memory device has a duty cycle correction circuit capable of outputting a duty cycle corrected clock and its inverted clock having substantially exactly 180° phase difference therebetween. The semiconductor memory device includes a duty cycle corrector configured to receive a first clock and a second clock to generate a first output clock and a second output clock whose duty cycle ratios are corrected in response to correction signals, and a clock edge detector configured to generate the correction signals corresponding to an interval between a reference transition timing of the first output clock and a reference transition timing of the second output clock.

摘要翻译： 半导体存储器件具有占空比校正电路，该电路能够输出占空比校正时钟及其倒相时钟，它们之间具有基本精确的180°相位差。 半导体存储器件包括占空比校正器，其被配置为接收第一时钟和第二时钟以产生第一输出时钟和响应校正信号校正其占空比的第二输出时钟;以及时钟沿检测器，被配置为产生 所述校正信号对应于所述第一输出时钟的参考转换定时与所述第二输出时钟的参考转换定时之间的间隔。

公开(公告)号：US08610468B2

公开(公告)日：2013-12-17

申请号：US13142079

申请日：2009-12-11

申请人： Hyun Soo Park ,  Byeong Cheon Jeong ,  Kyung Hoon Kim ,  Yeon Seok Song ,  Min Gyu Maing ,  Hong Chul Lee

发明人： Hyun Soo Park ,  Byeong Cheon Jeong ,  Kyung Hoon Kim ,  Yeon Seok Song ,  Min Gyu Maing ,  Hong Chul Lee

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： G06K7/0086

摘要： A power interface circuit of a contact integrated circuit (IC) card reader is provided. The power interface circuit includes a power control unit configured to invert, amplify and output a power control signal supplied from the outside, a switching diode unit configured to control on and off operations of a ground terminal transistor in a complementary transistor unit in response to an output signal of the power control unit, the complementary transistor unit in which complementary transistors transfer a power supply terminal voltage to a power output unit or mute a card power supply terminal of the power output unit to a ground voltage level while operating inversely to each other in response to a control signal directly input from the power control unit and a control signal input through the switching diode unit, and the power output unit configured to output a voltage input through the complementary transistor unit to a card power supply terminal of an IC card or maintain the card power supply terminal at the ground voltage level in response to operation of the complementary transistor unit.

摘要翻译： 提供了一种接触式集成电路（IC）读卡器的电源接口电路。 电源接口电路包括：功率控制单元，被配置为反相，放大和输出从外部提供的功率控制信号;开关二极管单元，被配置为响应于互补晶体管单元控制互补晶体管单元中的接地端子晶体管的导通和截止操作 功率控制单元的输出信号，互补晶体管单元，其中互补晶体管单元将电源端子电压传递到功率输出单元或将功率输出单元的卡电源端子静音到地电压电平，同时彼此反向工作 响应于从功率控制单元直接输入的控制信号和通过开关二极管单元输入的控制信号，以及功率输出单元，被配置为将通过互补晶体管单元输入的电压输出到IC卡的卡供电端子 或者将卡电源端子保持在接地电压水平，以响应补充的操作 内置晶体管单元。

公开(公告)号：US08509823B2

公开(公告)日：2013-08-13

申请号：US12089011

申请日：2006-09-25

申请人： Sung-Ho Hwang ,  Myoung-Gyu Son ,  Kyung-Hoon Kim ,  Sang-Man Bak

发明人： Sung-Ho Hwang ,  Myoung-Gyu Son ,  Kyung-Hoon Kim ,  Sang-Man Bak

IPC分类号： H04M3/42 ,  H04B7/216

CPC分类号： H04W4/18 ,  H04W4/14 ,  H04W88/184

摘要： A method for converting a SMS sent through a mobile communication network into a SMS or MMS in a previously registered format includes the steps of: receiving a SMS from a certain sending subscriber, determining whether the corresponding sending subscriber is subscribed to a SMS converting service, then converting the SMS into a previously registered format in case the sending subscriber is subscribed to the SMS converting service, and then sending the converted message to a designated receiving terminal.

摘要翻译： 用于将通过移动通信网络发送的SMS以预先注册的格式转换成SMS或MMS的方法包括以下步骤：从某个发送用户接收SMS，确定对应的发送用户是否订阅了SMS转换服务， 然后在发送订户订阅SMS转换服务的情况下将SMS转换成先前注册的格式，然后将转换的消息发送到指定的接收终端。

公开(公告)号：US08405437B2

公开(公告)日：2013-03-26

申请号：US13190079

申请日：2011-07-25

申请人： Kyung Hoon Kim

发明人： Kyung Hoon Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/087 ,  H03L7/0814 ,  H03L7/0816

摘要： A synchronization circuit includes a delay line, and a first loop and a second loop configured to share the delay line, and the second loop is activated when a number of unit delay cells used in the delay line is equal to or less than a predetermined number according to an operation of the first loop.

摘要翻译： 同步电路包括延迟线，以及被配置为共享延迟线的第一回路和第二回路，并且当延迟线中使用的单元延迟单元的数量等于或小于预定数量时，第二回路被激活 根据第一循环的操作。

公开(公告)号：US08284880B2

公开(公告)日：2012-10-09

申请号：US12005850

申请日：2007-12-28

申请人： Kyung-Hoon Kim ,  Jong-Ho Kang ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Sang-Yeon Byeon

发明人： Kyung-Hoon Kim ,  Jong-Ho Kang ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Sang-Yeon Byeon

IPC分类号： H04L7/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093

摘要： A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.

摘要翻译： 时钟数据恢复（CDR）电路占据了高集成度半导体器件，电子器件和系统所需的较小面积，并且易于进行设计修改。 CDR电路包括：数字滤波器，被配置为滤波在预定周期期间接收到的相位比较结果信号和输出控制信号;驱动器，被配置为通过调整预定周期来控制数字滤波器;以及输入/输出电路，被配置为识别输入和输出 的数据和时钟响应于控制信号。