公开(公告)号：US20040108540A1

公开(公告)日：2004-06-10

申请号：US10716703

申请日：2003-11-20

申请人： NEC ELECTRONICS CORPORATION

发明人： Akira Yoshino

IPC分类号： H01L029/788

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： The present invention provides nonvolatile semiconductor memory devices and methods for manufacturing thereof, which provide inhibiting the shortcutting of the channel due to the creation of the bird's beak to promote the manufacturing of the devices with higher-density or higher-integration, lowering the operation voltage and improving the characteristics of maintaining the electric charge, without complicating the manufacturing process. Immediately after forming an ONO films 3 comprising a first silicon oxide film 3a, a second silicon nitride film 3b and a third silicon oxide film 3c on a silicon substrate 1, a silicon layer 4 is formed, and then, arsenic ions are implanted over the silicon layer 4 and/or ONO films 3 to form a bit line, and a second electrical conductive layer 7 is deposited while remaining the silicon layer 4 to form a word line comprising a dual layer structure of two electrical conductive layers. This inhibits the generation of the bird's beak to liberalize the limitation to the miniaturization due to the effect of the shortcutting of the channel, and prevents the deterioration of the characteristic for maintaining electric charge. Further, the interface between the ONO films 3 and the silicon layer 4 is stabilized by having a configuration of remaining a portion of the silicon layer 4 in the channel region.

摘要翻译： 本发明提供了一种非易失性半导体存储器件及其制造方法，其特征在于，抑制由于形成鸟嘴而引起的通道的快捷性，以促进具有更高密度或更高集成度的器件的制造，降低了操作电压 并改善维持电荷的特性，而不会使制造过程复杂化。 在硅基板1上形成包含第一氧化硅膜3a，第二氮化硅膜3b和第三氧化硅膜3c的ONO膜3之后，立即形成硅层4，然后将砷离子注入 硅层4和/或ONO膜3以形成位线，并且在保留硅层4的同时沉积第二导电层7以形成包括两层导电层的双层结构的字线。 这抑制了鸟喙的产生，以便由于通道的快捷性的影响来放宽对小型化的限制，并且防止维持电荷的特性的劣化。 此外，通过在沟道区域中保留硅层4的一部分的结构，使ONO膜3和硅层4之间的界面稳定。

公开(公告)号：US20040108520A1

公开(公告)日：2004-06-10

申请号：US10688000

申请日：2003-10-17

申请人： NEC Electronics Corporation

发明人： Masayuki Furumiya ,  Hiroaki Ohkubo ,  Yasutaka Nakashiba

IPC分类号： H01L031/109

CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/088

摘要： The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a pnull diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.

摘要翻译： N型硅衬底的底侧连接到电源端子，在N型硅衬底的所有侧面上形成第二P型外延层，在第二P型外延层上设置器件形成部分。 第一P型外延层和层间绝缘膜设置在器件形成部分上，N阱和P阱形成在第一P型外延层的顶表面上。 第二P型外延层通过第一P型外延层，P阱，p +扩散区，通孔和导线连接到接地端子。 因此，在第二P型外延层和N型硅衬底之间的界面处形成pn结。

公开(公告)号：US20040099944A1

公开(公告)日：2004-05-27

申请号：US10687309

申请日：2003-10-16

申请人： NEC Electronics Corporation

发明人： Naoto Kimura

IPC分类号： H01L023/10

CPC分类号： H01L23/4334 ,  H01L25/0655 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2224/05599

摘要： A package is formed by mounting a plurality of semiconductor chips 6 and 7 on a substrate 1, arranging a heat spreader 13 on a resin surface opposite to a surface where pads 8 for the semiconductor chips are formed, via a curved intermediate plate 11 made of a metal, and filling with resin 14. The curved intermediate plate 11 is formed so as to easily bend in order to compensate the semiconductor chips 6 and 7 for the height difference relative to the heat spreader 13, and has a plurality of bumps 12 on the surface thereof in order to allow contact with the semiconductor chips by multipoint.

摘要翻译： 通过将多个半导体芯片6和7安装在基板1上，通过将形成有半导体芯片的焊盘8的表面相对的树脂表面上的散热器13经由弯曲的中间板11，由 金属，并填充树脂14.弯曲中间板11形成为容易弯曲，以补偿半导体芯片6和7相对于散热器13的高度差，并且具有多个凸起12 其表面为了允许通过多点与半导体芯片的接触。

公开(公告)号：US20040082101A1

公开(公告)日：2004-04-29

申请号：US10686568

申请日：2003-10-17

申请人： NEC Electronics Corporation

发明人： Hirokazu Honda

IPC分类号： H01L021/44

CPC分类号： H01L23/3171 ,  H01L23/293 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/274 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： In a flip-chip type semiconductor device, a plurality of pad electrodes are formed on a semiconductor substrate. An insulating stress-absorbing resin layer made of thermosetting resin is formed on the semiconductor substrate and has openings corresponding to the pad electrodes. A plurality of flexible conductive members are filled in the openings. A plurality of metal bumps are formed on the flexible conductive layers.

摘要翻译： 在倒装芯片型半导体器件中，在半导体衬底上形成多个焊盘电极。 在半导体衬底上形成由热固性树脂制成的绝缘应力吸收树脂层，并具有对应于焊盘电极的开口。 多个柔性导电构件填充在开口中。 在柔性导电层上形成多个金属凸块。

公开(公告)号：US20040081178A1

公开(公告)日：2004-04-29

申请号：US10691829

申请日：2003-10-23

申请人： NEC Electronics Corporation

发明人： Takashi Fujimori

IPC分类号： H04L012/28 ,  H04L012/56

CPC分类号： H04Q3/0058

摘要： A system including sub-networks mounted with different kinds of protocols/profiles, a gate way/proxy for connecting the sub-networks, a gate way/proxy for connecting the sub-networks, and nodes on the sub-networks, the gateway/proxy being mounted with processing of a physical layer and a data link layer as a protocol of the sub-network and processing of a physical layer and a data link layer as a protocol of the sub-network and having a common transport layer and a service proxy and a client proxy shared by the sub-networks.

摘要翻译： 一种系统，包括安装有不同种类的协议/简档的子网，用于连接子网的门方式/代理，用于连接子网的门方式/代理，以及子网上的节点，网关/ 代理正在以物理层和数据链路层的处理方式安装，作为子网络的协议，并且处理物理层和数据链路层作为子网络的协议并具有公共传输层和服务 代理和子网共享的客户端代理。

公开(公告)号：US20040080336A1

公开(公告)日：2004-04-29

申请号：US10606331

申请日：2003-06-26

申请人： NEC Electronics Corporation

发明人： Kazutoshi Hirano

IPC分类号： H03K019/003

CPC分类号： H03K19/0005

摘要： In an output buffer apparatus including a main-buffer circuit including a plurality of first transistors each connected between a first power supply terminal and an output terminal and a plurality of second transistors each connected between a second power supply terminal and the output terminal, and a pre-buffer circuit including a plurality of first pre-drivers each driving one of the first transistors in accordance with a data signal and a plurality of second pre-drivers each driving one of the second transistors in accordance with the data signal, a plurality of first sequential circuits are provided for receiving first impedance adjusting signals in synchronization with the data signal to turn ON the first pre-drivers, and a plurality of second sequential circuits are provided for receiving second impedance adjusting signals in synchronization with the data signal to turn ON the second pre-drivers.

摘要翻译： 在包括主缓冲电路的输出缓冲装置中，该主缓冲电路包括连接在第一电源端和输出端之间的多个第一晶体管，以及分别连接在第二电源端和输出端之间的多个第二晶体管， 预缓冲器电路包括多个第一预驱动器，每个第一预驱动器根据数据信号驱动第一晶体管中的一个;以及多个第二预驱动器，每个第二预驱动器根据数据信号驱动第二晶体管中的一个;多个第 提供第一顺序电路用于与数据信号同步地接收第一阻抗调整信号以接通第一预驱动器，并且提供多个第二顺序电路用于与数据信号同步接收第二阻抗调整信号以导通 第二个前驱动器。

公开(公告)号：US20040071189A1

公开(公告)日：2004-04-15

申请号：US10654126

申请日：2003-09-04

申请人： NEC ELECTRONICS CORPORATION

发明人： Nobue Tanaka

IPC分类号： G01K007/00

CPC分类号： G01K7/01 ,  G01K15/005

摘要： A temperature measuring sensor is incorporated in a substrate of a semiconductor device to measure a temperature of the substrate. The sensor has a diode formed in the substrate, and a resistor formed in the substrate and connected to the diode in series. When a first forward constant current is supplied to the diode through the resistor, a potential difference VA1 is produced between terminal ends of both the diode and the resistor connected in series, and a potential difference VF1 is produced between terminal ends of the diode. When a second forward constant current is supplied to the diode through the resistor, a potential difference VA2 is produced between the terminal ends of both the diode and the resistor connected in series, and a potential difference VF2 is produced between the terminal ends of the diode. A real temperature T of the substrate is calculated by the following formula: Tnull(q/k)(VF1nullVF2)null1/nullln((VA1nullVF1)/(VA2nullVF2))nullnullherein: T is an absolute temperature, k is Boltzmann's constant, and q is an electron charge.

摘要翻译： 温度测量传感器被结合在半导体器件的衬底中以测量衬底的温度。 该传感器具有形成在基板中的二极管，以及形成在基板中并与二极管串联连接的电阻器。 当通过电阻向二极管提供第一正向恒定电流时，在二极管和串联的电阻器的两端的端部之间产生电位差VA1，并且在二极管的端子之间产生电位差VF1。 当通过电阻向二极管提供第二正向恒定电流时，在二极管和串联连接的电阻器的端子之间产生电位差VA2，并且在二极管的端子之间产生电位差VF2 。 基板的实际温度T由下式计算：T =（q / k）（VF1-VF2）[1 / [ln（（VA1-VF1）/（VA2-VF2））]] 绝对温度，k是玻尔兹曼常数，q是电子电荷。

公开(公告)号：US20040071011A1

公开(公告)日：2004-04-15

申请号：US10648295

申请日：2003-08-27

申请人： NEC Electronics Corporation

发明人： Teiichiro Nishizaka ,  Isami Sakai ,  Akira Yoshino ,  Shinichi Kawai ,  Kiyokazu Ishige ,  Tomohiro Hamajima ,  Motoko Tanaka

IPC分类号： G11C011/00

CPC分类号： H01L27/11568 ,  G11C16/0416 ,  H01L27/115

摘要： A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film are included, wherein the first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines disposed on a layer overlying the semiconductor substrate. The second diffusion region is connected to a program and erase bit line disposed on a layer overlying the semiconductor substrate. Programming is performed to a selected memory cell transistor by hot electron injection, while erasing from the selected memory cell is performed by the hot hole injection.

摘要翻译： 半导体存储器件包括设置在第一和第二扩散区域之间的半导体衬底上的第一绝缘膜，设置在第一绝缘膜上的第一栅电极，设置在第二扩散区和第三扩散区之间的半导体衬底上的第二绝缘膜 并且包括设置在第二绝缘膜上的第二栅电极，其中第一和第二扩散区，第一绝缘膜和第一栅电极构成第一存储单元，而第二和第三扩散区，第二绝缘膜， 和第二栅电极构成第二存储单元。 第一和第二栅电极共同连接形成字线电极。 第一和第三扩散区域连接到布置在覆盖半​​导体衬底的层上的第一和第二读位线。 第二扩散区域连接到布置在覆盖半​​导体衬底的层上的编程和擦除位线。 通过热电子注入对所选择的存储单元晶体管进行编程，而通过热空穴注入执行从所选存储单元的擦除。

公开(公告)号：US20040060015A1

公开(公告)日：2004-03-25

申请号：US10658202

申请日：2003-09-10

申请人： NEC Electronics Corporation

发明人： Akira Mochizuki

IPC分类号： G06F017/50

CPC分类号： G06F9/30141

摘要： A register file includes a plurality of registers for storing therein data, a plurality of input ports for receiving therethrough the data to be stored in the registers, and a plurality of output ports for delivering therethrough the data stored in the registers. Each register includes an input port selector for selecting one of the write ports through which data is received. The register file also includes a read data selector block for specifying which data stored in the registers is to be read through one of the output ports. The output port selector is implemented by a combinational circuit which saves power dissipation of the register file.

摘要翻译： 寄存器文件包括用于在其中存储数据的多个寄存器，用于在其中接收要存储在寄存器中的数据的多个输入端口，以及用于在其中传送存储在寄存器中的数据的多个输出端口。 每个寄存器包括用于选择接收数据的写入端口之一的输入端口选择器。 寄存器文件还包括读取数据选择器块，用于指定通过其中一个输出端口读取寄存器中存储的数据。 输出端口选择器由组合电路实现，该组合电路节省了寄存器文件的功耗。

公开(公告)号：US20040059559A1

公开(公告)日：2004-03-25

申请号：US10668974

申请日：2003-09-24

申请人： NEC Electronics Corporation

发明人： Takashi Shimizu ,  Hironori Sakamoto

IPC分类号： G06F017/50

CPC分类号： G06F17/5036

摘要： From the data of diffusion-length-dependent parameters extracted from the parameters of the transistor model of MOS transistors and from the parameters of transistors having various diffusion lengths, a diffusion-length-dependent parameter correcting unit creates approximate expressions of the diffusion length dependence of these parameters, and calculates parameter correction values to be used instead of original parameter values by using the created approximate expressions. Hence, the correction values can be used easily instead of the original parameter values, whereby a transistor model of MOS transistors having a different diffusion length DL can be created easily. Circuit simulation in consideration of the diffusion length dependence of the drain currents of MOS transistors can thus be carried out, whereby highly accurate simulation can be attained.

摘要翻译： 根据从MOS晶体管的晶体管模型的参数和具有各种扩散长度的晶体管的参数提取的扩散长度相关参数的数据，扩散长度相关参数校正单元产生扩散长度依赖性的近似表达式 这些参数，并通过使用创建的近似表达式计算要使用的参数校正值而不是原始参数值。 因此，可以容易地使用校正值而不是原始参数值，由此可以容易地创建具有不同扩散长度DL的MOS晶体管的晶体管模型。 考虑到MOS晶体管的漏极电流的扩散长度依赖性的电路仿真可以进行，从而可以实现高精度的仿真。