TIME DIVISION MULTIPLEXING HUB
    102.
    发明公开

    公开(公告)号:US20240072922A1

    公开(公告)日:2024-02-29

    申请号:US17898335

    申请日:2022-08-29

    CPC classification number: H04J3/0685 H04J3/0617

    Abstract: An integrated circuit includes a control circuit, a primary sensor device coupled to the control circuit, and a plurality of groups of secondary sensor devices coupled to the primary sensor device. The primary sensor device receives a master clock signal from the control device and outputs, to each group of secondary sensor devices, a respective secondary clock signal with a frequency lower than the primary clock signal. The primary sensor device generates primary sensor data. The primary sensor device receives secondary sensor data from each group of secondary sensor devices. The primary sensor device combines the primary sensor data and all of the secondary sensor data into a sensor data stream with a time division-multiplexing scheme and outputs the sensor data stream to the control circuit.

    Method of manufacturing semiconductor devices and corresponding device

    公开(公告)号:US11901250B2

    公开(公告)日:2024-02-13

    申请号:US17411585

    申请日:2021-08-25

    CPC classification number: H01L23/3107 H01L21/561 H01L23/18 H01L23/49838

    Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pat gstern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.

    Low noise amplifier circuit for a thermal varying resistance

    公开(公告)号:US11894810B2

    公开(公告)日:2024-02-06

    申请号:US17952574

    申请日:2022-09-26

    CPC classification number: H03F1/26 H03F3/45192

    Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.

    Pulse generator circuit, related system and method

    公开(公告)号:US11894657B2

    公开(公告)日:2024-02-06

    申请号:US17360381

    申请日:2021-06-28

    CPC classification number: H01S5/06216 H01S5/0261 H03K5/07

    Abstract: An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.

    METHOD OF OPERATING HARD DISK DRIVES AND CORRESPONDING CONTROL CIRCUIT

    公开(公告)号:US20240038263A1

    公开(公告)日:2024-02-01

    申请号:US18354797

    申请日:2023-07-19

    CPC classification number: G11B5/54 H02P7/025

    Abstract: An embodiment method includes rectifying a back electromotive force of a spindle motor in a hard disk drive and energizing a voice coil motor in the hard disk drive using the rectified back electromotive force of the spindle motor via a voice coil motor power stage to retract a head of the hard disk drive to a park position. The head is retracted by moving the head towards the park position during a first retract phase and retaining the head in the park position during a second retract phase by applying a bias voltage to the voice coil motor power stage during a bias interval of the second retract phase. The method also includes producing a saturation signal indicative of onset of saturation in the voice coil motor power stage and controlling the bias voltage during the second retract phase.

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