公开(公告)号：US06928512B2

公开(公告)日：2005-08-09

申请号：US10163364

申请日：2002-06-06

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Tetsuya Iwamura ,  Kouichi Hoshi ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Tetsuya Iwamura ,  Kouichi Hoshi ,  Yoshikazu Saitou

IPC分类号： G11C11/41 ,  G06F12/00 ,  G06F12/06 ,  G11C5/00 ,  G11C11/00 ,  G11C11/401 ,  G11C11/406 ,  G11C11/408

CPC分类号： G11C11/4087 ,  G11C11/005 ,  G11C11/406 ,  G11C2207/2245 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/06135 ,  H01L2224/06156 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A non-volatile memory, an SRAM, a DRAM and a control circuit are module-formed into a single packaged. The control circuit assigns addresses to the SRAM and addresses to the DRAM and data necessary to be held for a long period of time is saved in the SRAM. Two chips of DRAM are mapped to the same address space and refreshed alternately. The plural chips are arranged such that they are mutually laminated, and they are wired by means of a BGA or inter-chip bonding.

摘要翻译： 非易失性存储器，SRAM，DRAM和控制电路被模块化成单个封装。 控制电路将地址分配给SRAM，并将DRAM的地址分配给SRAM，并将需要长时间保持的数据保存在SRAM中。 DRAM的两个芯片映射到相同的地址空间并交替刷新。 多个芯片被布置为使得它们相互层压，并且它们通过BGA或芯片间接合来布线。

公开(公告)号：US20050099876A1

公开(公告)日：2005-05-12

申请号：US11010324

申请日：2004-12-14

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F12/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4093 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。

公开(公告)号：US06847578B2

公开(公告)日：2005-01-25

申请号：US10729934

申请日：2003-12-09

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F12/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4093 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

公开(公告)号：US06791877B2

公开(公告)日：2004-09-14

申请号：US10164905

申请日：2002-06-10

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G11C1604

CPC分类号： G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

摘要翻译： 一种包括大容量非易失性存储器和至少一个随机存取存储器的半导体器件，所述设备的访问时间与每个随机存取存储器的访问时间相匹配。 半导体存储器件包括：具有第一读取时间的非易失性存储器FLASH; 具有比第一读取时间短100倍的第二读取时间的随机存取存储器DRAM; 电路，其包括连接到FLASH和DRAM两者的控制电路，并且能够控制对那些FLASH和DRAM的访问; 以及连接到电路的多个I / O端子。 结果，在访问DRAM之前，将FLASH数据传送到DRAM，从而与FLASH和DRAM之间的访问时间相匹配。 数据根据需要从DRAM写回到FLASH，从而保持FLASH和DRAM之间的数据匹配并存储数据。

公开(公告)号：US06708249B2

公开(公告)日：2004-03-16

申请号：US10101063

申请日：2002-03-20

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

IPC分类号： G06F1200

CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

公开(公告)号：US5752785A

公开(公告)日：1998-05-19

申请号：US527898

申请日：1995-09-14

申请人： Sadashi Tanaka ,  Seiji Miura ,  Kunio Takada ,  Masayuki Yamada ,  Yutaka Shimada ,  Akira Manabe

发明人： Sadashi Tanaka ,  Seiji Miura ,  Kunio Takada ,  Masayuki Yamada ,  Yutaka Shimada ,  Akira Manabe

IPC分类号： E03F1/00 ,  E03F5/10 ,  E03F5/22 ,  F04D15/00 ,  F02B11/00

CPC分类号： E03F5/22 ,  Y10T137/402

摘要： In a drainage pump station, a driving machine has a capacity greater than a shaft power necessary for no-discharge operation of a pump, and during severe flooding the pump is operated at an overload exceeding its design capacity. During maintenance operation water is fed from a river on the delivery side of the pump station into the station. When an inflow of rainwater into the pump station is great the pump is operated at the necessary capacity, when it becomes small the water level is kept above a rated value, and when the inflow rate is zero the pump discharge is increased to a capacity at which sediment can be discharged. A suction blower is disposed at the top of a suction sump and interstage valves are disposed in entrances of vertical shafts to effect efficient ventilation of the underground waterway. A feed channel is operated as a pressure channel and the pump is of variable capacity and the water level in the underground waterway is controlled to be constant.

摘要翻译： 在排水泵站中，驱动机器的容量大于泵的不排放操作所需的轴功率，并且在严重的淹水期间，泵以超过其设计能力的过载运行。 在维护作业过程中，水泵从泵站的输送侧的河流进入车站。 当雨水进入泵站的时候，泵的运行必须达到必要的水平，当水位变小时，水位保持在额定值以上，当流量为零时，泵排放量增加到 哪些沉积物可以排出。 抽吸鼓风机设置在吸入池的顶部，并且级间阀门设置在垂直轴的入口处，以实现地下水道的有效通风。 进料通道作为压力通道运行，泵具有可变容量，地下水路中的水位被控制为恒定。