公开(公告)号：US20080191285A1

公开(公告)日：2008-08-14

申请号：US11704402

申请日：2007-02-09

Applicant: Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7843

Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device are reduced by forming the PMOS device over a semiconductor layer having a low valence band.

Abstract translation: 半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源极/漏极延伸区域。 半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。 可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

公开(公告)号：US20070267694A1

公开(公告)日：2007-11-22

申请号：US11438711

申请日：2006-05-22

Applicant: Chih-Hsin Ko ,  Chung-Hu Ke ,  Hung-Wei Chen ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Chung-Hu Ke ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC: H01L29/76

CPC classification number: H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

Abstract: A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.

Abstract translation: 提供了在通道区​​域中具有优化的应力的MOS器件及其形成方法。 MOS器件包括在衬底上的栅极，栅极侧壁上的栅极间隔物，其中在栅极间隔物下方存在非硅化物区域，在衬底中包含凹陷的源极/漏极区域和源极上的硅化物区域 /漏区。 在硅化物区域的较高部分和硅化物区域的下部之间形成台阶高度。 凹槽与非硅化物区域的相应边缘间隔一定距离。 台阶高度和间距优选具有小于或等于约3的比率。非硅化物区域的宽度和台阶高度优选具有小于或等于约3的比率。MOS器件优选为 NMOS器件。

公开(公告)号：US07235838B2

公开(公告)日：2007-06-26

申请号：US10881372

申请日：2004-06-30

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee

IPC: H01L27/108

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10858 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/82

Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

Abstract translation: 一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。

公开(公告)号：US07208942B2

公开(公告)日：2007-04-24

申请号：US10991370

申请日：2004-11-19

Applicant: Wen-Chin Lee ,  Shang-Hao Chen

Inventor： Wen-Chin Lee ,  Shang-Hao Chen

IPC: G01B7/30 ,  G09G5/08

CPC classification number: G06F3/0362

Abstract: A precise, consistent, reliable, and high resolution magnetism metric controller applied in electronic and information devices is comprised of a scrolling wheel mechanism to drive by rotation a permanent magnet to retrieve signals of changed magnetic field due to displacement of magnetic poles of the permanent magnet.

Abstract translation: 应用于电子信息设备的精确，一致，可靠，高分辨率的磁力度量控制器包括一个滚动轮机构，通过旋转永久磁铁来驱动，以便通过永久磁铁的磁极位移来检索变化的磁场的信号 。

公开(公告)号：US07175709B2

公开(公告)日：2007-02-13

申请号：US10847099

申请日：2004-05-17

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: C30B25/04

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US20070018259A1

公开(公告)日：2007-01-25

申请号：US11187271

申请日：2005-07-21

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee

IPC: H01L29/94

CPC classification number: H01L21/823842 ,  H01L27/0922

Abstract: A semiconductor product includes a pair of field effect transistor device structures formed one each within a pair of doped well regions within a semiconductor substrate. The pair of field effect transistor device structures is formed with a pair of metal gate electrodes formed employing different laminated metal constructions. By correlating a work function within a metal layer within a gate electrode with a work function of a semiconductor substrate region over which it is formed, the field effect transistor devices are formed with enhanced performance.

Abstract translation: 半导体产品包括在半导体衬底内的一对掺杂阱区域内形成的一对场效应晶体管器件结构。 一对场效应晶体管器件结构由一对使用不同层压金属结构形成的金属栅电极形成。 通过将栅电极内的金属层中的功函数与形成在其上的半导体衬底区域的功函数相关联，形成具有增强性能的场效应晶体管器件。

公开(公告)号：US20060286740A1

公开(公告)日：2006-12-21

申请号：US11467980

申请日：2006-08-29

Applicant: Chun-Chieh LIN ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

Inventor： Chun-Chieh LIN ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC: H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US20060248239A1

公开(公告)日：2006-11-02

申请号：US11161785

申请日：2005-08-16

Applicant: Wen-Chin Lee ,  Chih-Sheng Huang

Inventor： Wen-Chin Lee ,  Chih-Sheng Huang

IPC: G06F3/00

CPC classification number: G01C21/30

Abstract: A data processing system includes a storage device which stores data, a processor which processes application programs and generates decision signals, a bus switch which is coupled with the storage device and the processor, and a processing chip which is coupled with the bus switch, the storage device, and the processor. The data processing system takes advantage of functions of playing media and processing application programs, wherein the functions are designed together with the processing chip. It is more powerful for combining both the functions to increase efficiency of the processor than general data processing system.

Abstract translation: 数据处理系统包括存储数据的存储装置，处理应用程序并产生决定信号的处理器，与存储装置和处理器耦合的总线开关，以及与总线开关耦合的处理芯片， 存储设备和处理器。 数据处理系统利用播放媒体和处理应用程序的功能，其中与处理芯片一起设计功能。 结合两种功能来提高处理器的效率比一般数据处理系统更强大。

公开(公告)号：US20060189056A1

公开(公告)日：2006-08-24

申请号：US11407633

申请日：2006-04-20

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/8234

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

Abstract: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

公开(公告)号：US20060091490A1

公开(公告)日：2006-05-04

申请号：US11077478

申请日：2005-03-10

Applicant: Hung-Wei Chen ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Min-Hwa Chi ,  Chung-Hu Ke

Inventor： Hung-Wei Chen ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Min-Hwa Chi ,  Chung-Hu Ke

IPC: H01L31/105

CPC classification number: H01L29/7391 ,  H01L29/868

Abstract: A gated p-i-n diode and a method for forming the same. The gated p-i-n diode comprises: a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode on the gate dielectric; a source gate spacer and a drain gate spacer along respective edges of the gate dielectric and the gate electrode; a source doped with a first type of dopant substantially under the source gate spacer wherein the source has a horizontal distance from a first edge of the gate electrode; a drain doped with the opposite type of the source substantially under the drain spacer and substantially aligned horizontally with a second edge of the gate electrode; a source silicide adjacent the source; and a drain silicide adjacent the drain.

Abstract translation: 门式p-i-n二极管及其形成方法。 门控p-i-n二极管包括：半导体衬底; 半导体衬底上的栅极电介质; 栅电极上的栅电极; 源栅极间隔物和漏极栅极间隔物，沿着栅极电介质和栅电极的相应边缘; 源极掺杂有基本上在源栅极间隔物下方的第一类型掺杂剂的源，其中源极与栅电极的第一边缘具有水平距离; 基本上在所述漏极间隔物的下方掺杂有相反类型的源极的漏极，并且与所述栅极电极的第二边缘基本对准; 邻近源极的源硅化物; 和漏极附近的漏极硅化物。