公开(公告)号：US20230185755A1

公开(公告)日：2023-06-15

申请号：US17644068

申请日：2021-12-13

Applicant: XILINX, INC.

Inventor： Sunita JAIN ,  Bharat Kumar GOGADA ,  Arjun VYNIPADATH ,  Meera BAGDAI

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/4063 ,  G06F2213/0026

Abstract: Embodiments herein describe using software or firmware to manage the device capability list of a PCIe device. That is, rather than relying on pure hardware to advertise the capabilities of a PCIe device, the embodiments herein permit software or firmware executing on a processor in the PCIe device to manage read and write requests associated with discovering the capabilities of the device and configuring the device.

公开(公告)号：US20230185548A1

公开(公告)日：2023-06-15

申请号：US17643622

申请日：2021-12-10

Applicant: Xilinx, Inc.

Inventor： Brian Guttag ,  Satish B. Sivaswamy ,  Nitin Deshmukh

IPC: G06F8/41

CPC classification number: G06F8/433

Abstract: Implementing an application can include generating, from the application, a compact data flow graph (DFG) including load nodes, inserting, in the compact DFG, a plurality of virtual buffer nodes (VBNs) for each of a plurality of buffers of a data processing engine (DPE) array to be allocated to nets of the application, and, forming groups of one or more load nodes of the compact DFG based on shared buffer requirements of the loads on a per net basis. Virtual driver nodes (VDNs) that map to drivers of nets can be added to the compact DFG, where each group of the compact DFG is driven by a dedicated VDN. Connections between VDNs and load nodes through selected ones of the VBNs are created according to a plurality of constraints. The plurality of buffers are allocated to the nets based on the compact DFG as connected.

公开(公告)号：US20230180379A1

公开(公告)日：2023-06-08

申请号：US17457595

申请日：2021-12-03

Applicant: XILINX, INC.

Inventor： Mohsen H. MARDI

IPC: H05K1/02

CPC classification number: H05K1/0203

Abstract: Micro devices having enhanced through heat transfer utilizing plungers extending from a heat spreader are provided. In one example, a micro device is provided that includes a plunger retaining block, a plurality of plungers, a mounting substrate and an integrated circuit (IC) die. The plunger retaining block includes a top surface and a bottom surface. The plurality of plungers extend from the bottom surface of the plunger retaining block with at least some of the plurality of plungers contacting the IC die. The IC die is disposed between the plunger retaining block and the mounting substrate, and coupled to the mounting substrate.

公开(公告)号：US11664800B1

公开(公告)日：2023-05-30

申请号：US16511925

申请日：2019-07-15

Applicant: Xilinx, Inc.

Inventor： VSS Prasad Babu Akurathi ,  Sabarathnam Ekambaram ,  Sasi Rama S. Lanka ,  Hari Bilash Dubey ,  Milind Goel

IPC: H03K17/687

CPC classification number: H03K17/6872

Abstract: A circuit for implementing an input/output connection in an integrated circuit device is described. The circuit comprises a pull-up circuit comprising a first plurality of transistors coupled in series, wherein a gate of a first transistor of the first plurality of transistors is configured to receive a first dynamic bias signal; a pull-down circuit comprising a second plurality of transistors coupled in series, the pull-down circuit being coupled to the pull-up circuit at an output node, wherein a gate of a first transistor of the second plurality of transistors is configured to receive a second dynamic bias signal; and an input/output contact coupled to the output node. A circuit for implementing an input/output connection in an integrated circuit device including a splitter circuit for receiving an input signal on an input pad is also described. A method of implementing an input/output connection in an integrated circuit device is also described.

公开(公告)号：US20230161569A1

公开(公告)日：2023-05-25

申请号：US17456002

申请日：2021-11-22

Applicant: Xilinx, Inc.

Inventor： Sumanta Datta ,  Srijan Tiwary ,  Aman Gayasen

IPC: G06F8/36 ,  G06F8/41 ,  G06F8/20 ,  G06F8/75

CPC classification number: G06F8/36 ,  G06F8/44 ,  G06F8/20 ,  G06F8/75

Abstract: Implementing an application for a data processing engine (DPE) array can include detecting, using computer hardware, a component of a hardware library package instantiated by an application. The application is specified in source code and is configured to execute on a DPE array. An instance of the component is extracted from the application. The extracted instance specifies values of parameters for the instance of the component. The instance can be partitioned by generating program code defining one or more kernels corresponding to the instance of the component. The partitioning is based on a defined performance metric of the component and a defined performance requirement of the application. The application is transformed by replacing the instance of the component with the program code generated by the partitioning. The application, as transformed, is compiled into program code executable by the DPE array.

公开(公告)号：US20230153156A1

公开(公告)日：2023-05-18

申请号：US17455074

申请日：2021-11-16

Applicant: Xilinx, Inc.

Inventor： Karthik Shankar ,  Jaideep Dastidar ,  Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F9/50

CPC classification number: G06F9/5027

Abstract: Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.

公开(公告)号：US20230127752A1

公开(公告)日：2023-04-27

申请号：US17511833

申请日：2021-10-27

Applicant: XILINX, INC.

Inventor： Roswald FRANCIS

IPC: H03K19/0185 ,  H03K19/00 ,  H03K19/17736 ,  H03K19/17788

Abstract: Techniques and apparatus for reducing low frequency power supply spurs in clock signals in a clock distribution network. One example circuit for clock distribution generally includes a plurality of logic inverters coupled in series and configured to drive a clock signal and a current-starved inverter coupled in parallel (or in series) with a logic inverter in the plurality of logic inverters.

公开(公告)号：US20230113197A1

公开(公告)日：2023-04-13

申请号：US17498048

申请日：2021-10-11

Applicant: Xilinx, Inc.

Inventor： Amit Kasat ,  Tharun Kumar Ksheerasagar ,  Hemant Kashyap ,  Madhusudana Reddy ,  Rohit Bhadana

IPC: G06F30/3308 ,  G06F30/323

Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server. The communication layer client provides an application programming interface through which an external computer program generates data traffic to drive the DUT within the simulation.

公开(公告)号：US20230094621A1

公开(公告)日：2023-03-30

申请号：US17449561

申请日：2021-09-30

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  James MURRAY

IPC: G06F12/0817

Abstract: Embodiments herein describe memories in a processor system in an integrated circuit (IC) that can be assigned to either a cache coherent domain or an I/O domain, rather than being statically assigned by a designer of the IC. That is, the user or customer can assign the memories to domain that best suits their desires. Further, the memories can be reassigned to a different domain if the user later changes her mind.

公开(公告)号：US11615300B1

公开(公告)日：2023-03-28

申请号：US16007884

申请日：2018-06-13

Applicant: Xilinx, Inc.

Inventor： Julian Faraone ,  Michaela Blott ,  Nicholas Fraser

IPC: G06N3/08 ,  G06N3/04

Abstract: A neural network system includes an input layer, one or more hidden layers, and an output layer. A first layer circuit implements a first layer of the one or more hidden layers. The first layer includes a first weight space including one or more subgroups. A forward path circuit of the first layer circuit includes a multiply and accumulate circuit to receive an input from a layer preceding the first layer; and provide a first subgroup weighted sum using the input and a first plurality weights associated with a first subgroup. A scaling coefficient circuit provides a first scaling coefficient associated with the first subgroup, and applies the first scaling coefficient to the first subgroup weighted sum to generate a first subgroup scaled weighted sum. An activation circuit generates an activation based on the first subgroup scaled weighted sum and provide the activation to a layer following the first layer.