公开(公告)号：US10095421B2

公开(公告)日：2018-10-09

申请号：US15331582

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10

Abstract: Systems, apparatuses, and methods for implementing a hybrid memory module bridge network and buffers are disclosed. A system includes one or more host processors and multiple memory modules. Each memory module includes a relatively low pin count, high-bandwidth serial link to one or more other memory modules to perform inter-memory data transfers without consuming host-memory bandwidth. In one embodiment, a first memory module acts as a cache and a second memory module acts as the main memory for the system. The traffic between the host and the first memory module utilizes a first interface, and the cache traffic between the first and second memory modules utilizes a second interface. Cache line fill and writeback transfers between the first and second memory modules occur in parallel with timing-critical cache demand accesses from the host, in a latency-tolerant and buffered manner, without interfering with the cache demand accesses.

公开(公告)号：US10079916B2

公开(公告)日：2018-09-18

申请号：US15138485

申请日：2016-04-26

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Kevin Y. Cheng ,  Nathan Hu

IPC: H04L29/06 ,  G06F9/00 ,  G06F13/00 ,  H04L12/741

CPC classification number: H04L69/04 ,  G06F9/00 ,  G06F13/00 ,  H04L45/74

Abstract: Systems, apparatuses, and methods for reducing inter-node bandwidth are contemplated. A computer system includes requesting nodes sending transactions to target nodes. A requesting node sends a packet that includes a register identifier (ID) in place of a data value in the packet. The register ID indicates a register in the target node storing the data value. The register ID uses fewer bits in the packet than the data value. The data value may be a memory address referencing a memory location in the target node. The received packet may also include an opcode indicating an operation to perform on the targeted data value.

公开(公告)号：US20180113628A1

公开(公告)日：2018-04-26

申请号：US15331582

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F13/14

Abstract: Systems, apparatuses, and methods for implementing a hybrid memory module bridge network and buffers are disclosed. A system includes one or more host processors and multiple memory modules. Each memory module includes a relatively low pin count, high-bandwidth serial link to one or more other memory modules to perform inter-memory data transfers without consuming host-memory bandwidth. In one embodiment, a first memory module acts as a cache and a second memory module acts as the main memory for the system. The traffic between the host and the first memory module utilizes a first interface, and the cache traffic between the first and second memory modules utilizes a second interface. Cache line fill and writeback transfers between the first and second memory modules occur in parallel with timing-critical cache demand accesses from the host, in a latency-tolerant and buffered manner, without interfering with the cache demand accesses.

公开(公告)号：US20180081590A1

公开(公告)日：2018-03-22

申请号：US15273013

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini Farahani ,  David A. Roberts ,  Nuwan Jayasena

IPC: G06F3/06 ,  G06F12/0802 ,  G06F13/16

CPC classification number: G06F13/1673 ,  G06F12/0802 ,  G06F2212/60 ,  Y02D10/14

Abstract: A processing system employs a memory module as a temporary write buffer to store write requests when a write buffer at a memory controller reaches a threshold capacity, and de-allocates the temporary write buffer when the write buffer capacity falls below the threshold. Upon receiving a write request, the memory controller stores the write request in a write buffer until the write request can be written to main memory. The memory controller can temporarily extend the memory controller's write buffer to the memory module, thereby accommodating temporary periods of high memory activity without requiring a large permanent write buffer at the memory controller.

公开(公告)号：US20170371720A1

公开(公告)日：2017-12-28

申请号：US15191355

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Dmitri Yudanov ,  David A. Roberts ,  Mitesh R. Meswani ,  Sergey Blagodurov

IPC: G06F9/52

Abstract: A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. The controller is further configured to provide the determined lagging task to a second processor to be executed by the second processor to accelerate execution of the lagging task.

公开(公告)号：US20170364262A1

公开(公告)日：2017-12-21

申请号：US15184996

申请日：2016-06-16

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0616 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/068 ,  G06F3/0688

Abstract: A memory system includes a write buffer, a main memory having a higher latency than the write buffer, and a memory controller. In response to a write request indicating first data for storing at a write address in the main memory, the memory controller adds a new write entry in the write buffer, where the new write entry includes the write address and the first data, and updates a pointer of a previous write entry in the write buffer to point to the new write entry. In response to a write-back instruction, the memory controller traverses a plurality of write entries stored in the write buffer, and writes into the main memory second data of the previous write entry and the first data of the new write entry.

公开(公告)号：US09811456B2

公开(公告)日：2017-11-07

申请号：US14554972

申请日：2014-11-26

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F2212/7211

Abstract: In one form, a data processor comprises a memory accessing agent and a memory controller. The memory accessing agent selectively initiates read accesses to and write accesses from a memory. The memory controller is coupled to the memory accessing agent and is adapted to be coupled to the memory and to access the memory using a start-gap wear-leveling algorithm. The memory controller is adapted to maintain a metadata log in a region of the memory and to store in the metadata log a start address and a gap address used in the start-gap wear-leveling algorithm, and upon initialization to access the metadata log to retrieve an initial start address and an initial gap address for use in the start-gap wear-leveling algorithm. In another form, a memory module may comprise a memory buffer including such a memory controller.

公开(公告)号：US20170168546A1

公开(公告)日：2017-06-15

申请号：US14963352

申请日：2015-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Dmitri Yudanov ,  Arkaprava Basu ,  Sergey Blagodurov

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/3243 ,  G06F9/3885

Abstract: A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.

公开(公告)号：US20170147228A1

公开(公告)日：2017-05-25

申请号：US14952517

申请日：2015-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Sergey Blagodurov ,  David A. Roberts ,  Mitesh R. Meswani ,  Nuwan Jayasena ,  Michael Ignatowski

IPC: G06F3/06

CPC classification number: G06F12/08 ,  G06F12/0811 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/4022 ,  G06F15/7821 ,  G06F2212/1024

Abstract: A plurality of memory blocks are connected to a computation-enabled switch that provides data paths between the plurality of memory blocks. The computation-enabled switch performs one or more computations on data stored in one or more of the plurality of memory blocks during transfer of the data along one or more of the data paths between the plurality of memory blocks.

公开(公告)号：US20170123987A1

公开(公告)日：2017-05-04

申请号：US14928981

申请日：2015-10-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin Y. Cheng ,  David A. Roberts

IPC: G06F12/08 ,  G06F13/42

CPC classification number: G06F12/0862 ,  G06F9/4401 ,  G06F13/42 ,  G06F15/7821 ,  G06F2212/1024 ,  G06F2212/45

Abstract: Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.