Abstract:
Methods and devices useful in discharging an aberrant charge on a touch sensitive display of an electronic device are provided. By way of example, a an electronic device includes a power management and control circuitry configured to receive a first voltage signal and a second voltage signal from a display subsystem of a display of the electronic device, receive a third voltage signal from a touch subsystem of the display, provide a power signal to the display subsystem to activate the display subsystem when the display is determined to be in a temporarily inactive state. Providing the power signal to the display subsystem comprises discharging an aberrant charge based on the third voltage signal.
Abstract:
A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.
Abstract:
An organic light-emitting diode display may have an array of pixels. The pixels may each have an organic light-emitting diode with a respective anode and may be formed from thin-film transistor circuitry formed on a substrate. A mesh-shaped path may be used to distribute a power supply voltage to the thin-film circuitry. The mesh-shaped path may have intersecting horizontally extending lines and vertically extending lines. The horizontally extending lines may be zigzag metal lines that do not overlap the anodes. The vertically extending lines may be straight vertical metal lines that overlap the anodes. The pixels may include pixels of different colors. Angularly dependent shifts in display color may be minimized by ensuring that the anodes of the differently colored pixels overlap the vertically extending lines by similar amounts.
Abstract:
An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be enabled to emit light in each frame. In the partial scanning mode, only a subset of the rows of the display may be enabled to emit light in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. To ensure uniform transistor stress across the display, the scanning driver for the display may scan the disabled rows in the partial scanning mode even though the rows will not be used to emit light.
Abstract:
A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse is that received through a demultiplexing circuit. In another suitable embodiment, the gate driver circuit may include analog or digital gate driver units that include control circuits for selectively (dis)charging internal nodes in the gate driver circuit so as to balance the amount of stress that is experienced by a drive transistor in gate driver units at or near an IFP row and the amount of stress that is experienced by the remaining gate driver units.
Abstract:
A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver may be operable in a high impedance mode, where the output of the gate driver is left floating during touch or IFP intervals. In another suitable arrangement, the gate driver may be operable in an IFP reduced stress mode, where a digital pass gate in the gate driver is deactivated during IFP intervals. In yet another suitable arrangement, the gate driver may be operable in an all-gate-high (AGH) power-down mode, where the output of each gate driver in the driver circuitry is driven high in parallel when the displayed is being powered off. These arrangements may be implemented in any suitable combination.
Abstract:
A display may have an active area surrounded by a border area. The display may be a liquid crystal display having a liquid crystal layer sandwiched between a color filter layer and a thin-film transistor layer. The liquid crystal layer may be retained within the display using a ring of sealant that is dispensed along the border area on the thin-film transistor layer. The thin-film transistor layer may include at least a substrate, a dielectric layer formed over the substrate, a first planarization layer formed on the dielectric layer, and a second planarization layer formed on the first planarization layer. A first continuous trench structure may be formed along the border of the display to help prevent moisture seepage. A second trench structure that is separate from the first trench structure may be formed along the border of the display to help provide proper sealant adhesion.
Abstract:
A display may have an array of pixels controlled by display driver circuitry. The pixels may have pixel circuits. In liquid crystal display configurations, each pixel circuit may have an electrode that applies electric fields to an associated portion of a liquid crystal layer. In organic light-emitting diode displays, each pixel circuit may have a drive transistor that applies current to an organic light-emitting diode in the pixel circuit. The pixel circuits and display driver circuitry may have thin-film transistor circuitry that includes transistor such as silicon transistors and semiconducting-oxide transistors. Semiconducting-oxide transistors and silicon transistors may be formed on a common substrate. Semiconducting-oxide transistors may have polysilicon layers with doped regions that serve as gates. Semiconducting-oxide channel regions overlap the gates. Transparent conductive oxide and metal may be used to form source-drain terminals that are coupled to opposing edges of the semiconducting oxide channel regions.
Abstract:
An electronic display system has a light transmissive panel, a region of display elements on the panel, and source lines coupled to the display elements. A demultiplexer circuit has multiple groups of pass gates. Each pass gate has a pair of complimentary on-panel transistors, and the signal outputs of each group are connected to a respective group of the source lines. A display driver integrated circuit (IC) receives video data and timing control signals. A signal input of each group of pass gates is connected to a respective output pin of the driver IC. The display driver IC provides digital timing control signals to control the pass gates of the demultiplexer circuit. Other embodiments are also described.
Abstract:
A display may have a thin-film-transistor layer with a substrate layer. A layer of dielectric may be formed on the substrate layer and may have an upper surface and a lower surface. The thin-film-transistor layer may include an array of display pixels. Data lines and gate lines may provide signals to the display pixels. Gate driver circuitry in an inactive peripheral portion of the display may include a gate driver circuit for each gate line. The gate driver circuits may include thin-film transistors that are formed on the upper surface of the layer of dielectric. Signal lines such as a gate low line, a gate routing line coupled between the gate driver circuits, and a common electrode line may be formed from two or more layers of metal to reduce their widths or may be embedded within the dielectric layer between the upper and lower surfaces under the thin-film transistors.