公开(公告)号：US06673682B2

公开(公告)日：2004-01-06

申请号：US10144874

申请日：2002-05-13

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L218236

CPC classification number: H01L27/11253 ,  H01L27/112 ,  H01L27/1126

Abstract: Methods for making integrated circuit devices, such as high density memory devices and memory devices exhibiting dual bits per cell, include forming multiple oxide fences on a semiconductor substrate between multiple polybars. The oxide fences create a hole pre-code pattern that facilitates ion implantation into trenches disposed between the polybars. The holes, or voids, formed by the oxide fences provide greater control of the critical dimension of ion implantation, for example, the critical dimension of the trench sidewalls. Semiconductor devices used in the manufacture of memory devices include the oxide fences during the manufacturing process.

Abstract translation: 用于制造诸如高密度存储器件和表现出每个单元双位的存储器件的集成电路器件的方法包括在多个多边形之间的半导体衬底上形成多个氧化物围栅。 氧化物栅栏产生一个孔预编码图案，便于将离子注入到设置在多边形之间的沟槽中。 由氧化物栅栏形成的孔或空隙提供了对离子注入的关键尺寸（例如沟槽侧壁的临界尺寸）的更大控制。 用于制造存储器件的半导体器件包括在制造过程中的氧化物栅栏。

公开(公告)号：US06607674B2

公开(公告)日：2003-08-19

申请号：US09726459

申请日：2000-11-30

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: B81B702

CPC classification number: C03C17/3649 ,  C03C17/3435 ,  C03C17/36 ,  C03C17/3665 ,  C03C2218/33 ,  G03F1/32 ,  G03F1/72

Abstract: A phase shifting mask repair process is described. The process uses an etching gas or a hydrofluoric acid solution to etch the quartz substrate and the characteristics of the phase shifter layer being only slightly etched when clean with a NH3/H2O2/H2O2 solution to calculate and adjust the respective processing time accordingly. As a result, the phase difference between the quartz substrate and the MoSiON phase shifter layer stays relatively the same before and after the repair process.

公开(公告)号：US06569761B2

公开(公告)日：2003-05-27

申请号：US09903667

申请日：2001-07-13

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L214763

CPC classification number: H01L21/0337 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/0338 ,  H01L21/76816

Abstract: In accordance with the present invention, a method is provided for shrinking critical dimension in semiconductor processes. This method comprises a step of performing an over-exposure process to a photosensitive layer to form a patterned photosensitive layer on a substrate by using a patterned reticle. Due to the unexposed region of the photosensitive layer being diminished by over-exposure the critical dimension is shrunk. Then, a sacrificial layer is applied for the purpose of pattern reverse-transferring. Next, the patterned photosensitive layer is removed such that the pattern is transferred to the sacrificial layer with a shrunk critical dimension. In cooperation of the present exposure technology with the present invention, the shrinkage of a critical dimension is accomplished, for example, using an I-line exposure light source in a critical dimension of 0.25 &mgr;m process, or using a deep UV (ultraviolet) exposure light source in a critical dimension of 0.13 &mgr;m process.

公开(公告)号：US06562691B2

公开(公告)日：2003-05-13

申请号：US09799003

申请日：2001-03-06

Applicant: Ching-Yu Chang ,  Wei-Hwa Sheu

Inventor： Ching-Yu Chang ,  Wei-Hwa Sheu

IPC: H01L2176

CPC classification number: G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A method for forming a protrusive alignment-mark in semiconductor devices is disclosed. A photolithography process is performed to form a photoresist layer on a substrate wherein the substrate has an element region and an alignment region, and the photoresist layer has an element photoresist region and an alignment photoresist region. Afterwards, a first dielectric layer is deposited on the element photoresist region and the alignment photoresist region. The excess portion of first dielectric layer above the photoresist layer is removed such that the photoresist layer is coplanar with the first dielectric layer and thus the photoresist layer is exposed. The photoresist layer on the element region and said alignment region is stripped to form a protrusive alignment-mark on the alignment region.

公开(公告)号：US06448605B1

公开(公告)日：2002-09-10

申请号：US09924904

申请日：2001-08-08

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L2976

CPC classification number: H01L28/92 ,  H01L21/28273 ,  H01L21/32139 ,  H01L29/66545

Abstract: A method of fabricating a gate is described. A first dielectric layer having a first opening is formed on a substrate. A gate dielectric layer is formed in the opening. A lower portion of a floating gate is formed on the gate dielectric layer. A source/drain region is formed in the substrate beside the lower portion of the floating gate. A conductive layer is formed on the first dielectric layer to completely fill the first opening. The conductive layer is patterned to form a second opening in the conductive layer. The second opening is above the first opening and does not expose the first dielectric layer. The second opening has a tapered sidewall and a predetermined depth. A mask layer is formed to cover the conductive layer and fill the second opening. The mask layer outside the second opening is removed to expose the conductive layer. A portion of the mask layer is removed to leave a first etching mask layer in the second opening. An anisotropic etching process using the first etching mask layer as a mask is performed to etch the conductive layer. An upper portion of the floating gate is formed. The first dielectric layer is exposed. The first etching mask is removed. Thereafter, a dielectric layer between gates and a control gate is formed over the floating gate.

公开(公告)号：US09851636B2

公开(公告)日：2017-12-26

申请号：US13542160

申请日：2012-07-05

Applicant: Chen-Yu Liu ,  Ching-Yu Chang

Inventor： Chen-Yu Liu ,  Ching-Yu Chang

IPC: G03F7/004 ,  G03F7/016 ,  G03F7/038 ,  G03F7/039

CPC classification number: G03F7/0045 ,  G03F7/0163 ,  G03F7/0382 ,  G03F7/0392

Abstract: A photosensitive material and methods of making a pattern on a substrate are disclosed. The photosensitive material includes a polymer that turns soluble to a developer solution after a chemically amplified reaction, and at least one chemical complex having a single diffusion length. The material includes at least one photo-acid generator (PAG) linked to at least one photo decomposable base (PDB) or quencher.

公开(公告)号：US09261786B2

公开(公告)日：2016-02-16

申请号：US13437674

申请日：2012-04-02

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: G03F7/00 ,  G03F7/039 ,  G03F7/20 ,  G03F7/26 ,  G03F7/32

CPC classification number: G03F7/0397 ,  G03F7/2041 ,  G03F7/26 ,  G03F7/325

Abstract: Methods and materials directed to solubility of photosensitive material in negative tone developer are described. The photosensitive material may include greater than 50% acid labile groups as branches to a polymer chain. In another embodiment, a photosensitive material, after exposure or irradiation, is treated. Exemplary treatments include applying a base to the photosensitive material.

Abstract translation: 描述了涉及感光材料在负色调显影剂中的溶解度的方法和材料。 感光材料可以包括大于50％的酸不稳定基团作为聚合物链的分支。 在另一个实施方案中，在曝光或照射之后对感光材料进行处理。 示例性的处理包括将基底施加到感光材料上。

公开(公告)号：US08741551B2

公开(公告)日：2014-06-03

申请号：US13442687

申请日：2012-04-09

Applicant: Chen-Hau Wu ,  Ching-Yu Chang

Inventor： Chen-Hau Wu ,  Ching-Yu Chang

IPC: G03F7/26

CPC classification number: G03F7/095 ,  G03F7/0045 ,  G03F7/0392

Abstract: The present disclosure provides a sensitive material. The sensitive material includes a polymer that turns soluble to a base solution in response to reaction with acid; a plurality of photo-base generators (PBGs) that decompose to form base in response to radiation energy; and a thermal sensitive component that generates acid in response to thermal energy.

Abstract translation: 本公开提供敏感材料。 敏感材料包括响应于与酸的反应而将可溶于碱溶液的聚合物; 响应于辐射能分解形成底座的多个光源发生器（PBG）; 以及响应于热能产生酸的热敏组分。

公开(公告)号：US20130210232A1

公开(公告)日：2013-08-15

申请号：US13369818

申请日：2012-02-09

Applicant: Ho Wei De ,  Kuei-Liang Lu ,  Ming-Feng Shieh ,  Ching-Yu Chang

Inventor： Ho Wei De ,  Kuei-Liang Lu ,  Ming-Feng Shieh ,  Ching-Yu Chang

IPC: H01L21/311 ,  C23C16/04 ,  B44C1/22

CPC classification number: G03F1/38 ,  G03F7/70466 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/845 ,  H01L27/1211

Abstract: A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer.

Abstract translation: 用于图案化非矩形图案中的多个特征的方法，例如在集成电路器件上，包括提供包括具有多个细长突起的表面的基底，所述细长突起沿第一方向延伸。 第一层形成在多个细长突起的表面上方和上方，并用端部切割掩模图案化。 末端切割掩模包括两个几乎相邻的图案，其具有定位和配置的次分辨率特征，使得当第一层上的所得图案包括两个近似相邻的图案时，以及其间的连接。 该方法还包括使用第一层上的图案切割细长突起的端部。

公开(公告)号：US20130203257A1

公开(公告)日：2013-08-08

申请号：US13368144

申请日：2012-02-07

Applicant: Ho Wei De ,  Ming-Feng Shieh ,  Ching-Yu Chang

Inventor： Ho Wei De ,  Ming-Feng Shieh ,  Ching-Yu Chang

IPC: H01L21/302 ,  H01L31/18

CPC classification number: H01L21/845 ,  G03F1/00 ,  H01L21/823431

Abstract: A method for patterning a plurality of features in a non-rectangular pattern on an integrated circuit device includes providing a substrate including a surface with a first layer and a second layer, forming a plurality of elongated protrusions in a third layer above the first and second layers, and forming a first patterned layer over the plurality of elongated protrusions. The plurality of elongated protrusions are etched to form a first pattern of the elongated protrusions, the first pattern including at least one inside corner. The method also includes forming a second patterned layer over the first pattern of elongated protrusions and forming a third patterned layer over the first pattern of elongated protrusions. The plurality of elongated protrusions are etched using the second and third patterned layers to form a second pattern of the elongated protrusions, the second pattern including at least one inside corner.

Abstract translation: 一种用于在集成电路器件上以非矩形图案形成多个特征的方法包括提供包括具有第一层和第二层的表面的衬底，在第一和第二层上方的第三层中形成多个细长突起 层，并且在所述多个细长突起上形成第一图案化层。 多个细长突起被蚀刻以形成细长突起的第一图案，第一图案包括至少一个内角。 该方法还包括在细长突起的第一图案上方形成第二图案化层，并在第一图案的细长突起上形成第三图案化层。 使用第二和第三图案化层来蚀刻多个细长突起，以形成细长突起的第二图案，第二图案包括至少一个内角。