公开(公告)号：US10410929B2

公开(公告)日：2019-09-10

申请号：US15860840

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jianwei Peng ,  Yi Qi ,  Hsien-Ching Lo ,  Jerome Ciavatti ,  Ruilong Xie

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66 ,  H01L21/20

Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.

公开(公告)号：US10373877B1

公开(公告)日：2019-08-06

申请号：US15986390

申请日：2018-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Hui Zang ,  Wei Zhao ,  Yue Zhong ,  Guowei Xu ,  Laertis Economikos ,  Jerome Ciavatti ,  Scott Beasor

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities. In this example, the method also includes, after forming the contact isolation structures, removing the sacrificial gate structures so as to form a plurality of replacement gate cavities, and forming a final gate structure in each of the plurality of replacement gate cavities.

公开(公告)号：US10283423B2

公开(公告)日：2019-05-07

申请号：US15292184

申请日：2016-10-13

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC: H01L21/66 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

公开(公告)号：US20190131424A1

公开(公告)日：2019-05-02

申请号：US15801722

申请日：2017-11-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei Xu ,  Suraj K. Patil ,  Hui Zang ,  Katsunori Onishi ,  Keith H. Tabakman

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: The present disclosure relates to methods for forming IC structures having recessed gate spacers and related IC structures. A method may include: forming a first and second dummy gate over a fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer and a second gate spacer, the opening exposing a source/drain region; recessing the first and second gate spacers; forming an etch stop layer within the opening such that the etch stop layer extends vertically along the recessed first and second gate spacers; forming a dielectric fill over the etch stop layer to substantially fill the opening; replacing the first and second dummy gates with first and second RMG structures; recessing the first and second RMG structures; and forming a gate cap layer over the first and second RMG structures.

公开(公告)号：US10276689B2

公开(公告)日：2019-04-30

申请号：US15615925

申请日：2017-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Ruilong Xie ,  Xunyuan Zhang ,  Hui Zang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.

公开(公告)号：US20190123160A1

公开(公告)日：2019-04-25

申请号：US16190549

申请日：2018-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Julien Frougier ,  Hui Zang ,  Min-hwa Chi

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786

Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

公开(公告)号：US20190103319A1

公开(公告)日：2019-04-04

申请号：US15723472

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Wei Hong ,  Yanping Shen ,  Yongjun Shi ,  Hui Zang ,  Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/088

Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.

公开(公告)号：US10249538B1

公开(公告)日：2019-04-02

申请号：US15723472

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Wei Hong ,  Yanping Shen ,  Yongjun Shi ,  Hui Zang ,  Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/311

Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.

公开(公告)号：US20190043965A1

公开(公告)日：2019-02-07

申请号：US16147072

申请日：2018-09-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-Hwa Chi ,  Jinping Liu

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the second region.

公开(公告)号：US20190043758A1

公开(公告)日：2019-02-07

申请号：US15670366

申请日：2017-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Keith Tabakman ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/283 ,  H01L21/768

Abstract: Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative method disclosed herein includes performing at least one first etching process to form a recess in a gate structure of a gate of a transistor device so as to expose an innermost surface of a portion of a sidewall spacer positioned adjacent a first sidewall of the gate structure and performing at least one second etching process through at least the recess in the gate structure so as to remove at least a portion of the portion of the sidewall spacer with the exposed innermost surface.