公开(公告)号：US20210063655A1

公开(公告)日：2021-03-04

申请号：US16559979

申请日：2019-09-04

Applicant: GLOBALFOUNDRIES Inc. ,  KHALIFA UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Sujith Chandran ,  Marcus Dahlem ,  Ajey Poovannummoottil Jacob ,  Yusheng Bian ,  Bruna Paredes ,  Jaime Viegas

IPC: G02B6/42 ,  G02B6/293

Abstract: Structures for a wavelength-division multiplexing filter and methods of fabricating a structure for a wavelength-division multiplexing filter. The structure includes a first waveguide core, a second waveguide core laterally spaced from the first waveguide core, and a ring resonator arranged in a vertical direction over the first waveguide core and the second waveguide core. The ring resonator is also arranged in a lateral direction between the first waveguide core and the second waveguide core. The first and second waveguide cores are composed of a semiconductor material, such as single-crystal silicon, and the ring resonator is composed of a dielectric material, such as silicon nitride.

公开(公告)号：US20210055478A1

公开(公告)日：2021-02-25

申请号：US16549197

申请日：2019-08-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/122 ,  G02B6/30 ,  G02B6/136

Abstract: Structures for a waveguide coupler and methods of fabricating a structure for a waveguide coupler. A first waveguide core has a first width, a second waveguide core has a second width less than the first width, and a waveguide coupler includes first and second tapers that are positioned between the first waveguide core and the second waveguide core. The second taper is directly connected with the first taper, and the first and second tapers connect the first and second waveguide cores.

公开(公告)号：US10818807B2

公开(公告)日：2020-10-27

申请号：US16253191

申请日：2019-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Theodore J. Letavic ,  Abu Thomas ,  Yusheng Bian

IPC: H01L31/02 ,  H01L31/18 ,  G02B1/11 ,  G02B5/08 ,  H01L31/0232 ,  H01L31/0216 ,  G02B1/113

Abstract: The present disclosure generally relates to semiconductor detectors for use in optoelectronic devices and integrated circuit (IC) chips, and methods for forming same. More particularly, the present disclosure relates to integration of semiconductor detectors with Bragg reflectors. The photodetector of the present disclosure includes a substrate, a Bragg reflector disposed on the substrate, and a semiconductor detector disposed on the Bragg reflector. The Bragg reflector includes alternating layers of a semiconductor material and a dielectric material.

公开(公告)号：US10816727B1

公开(公告)日：2020-10-27

申请号：US16441678

申请日：2019-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/125 ,  G02B6/136 ,  G02B6/12

Abstract: Structures for a waveguide bend and methods of fabricating a structure for a waveguide bend. A waveguide core has a first section, a second section, and a waveguide bend connecting the first section with the second section. The waveguide core includes a first side surface and a second side surface, the first side surface extends about an inner radius of the waveguide bend, and the second side surface extends about an outer radius of the waveguide bend. The waveguide bend includes a central region and a side region that is arranged adjacent to the central region at the first side surface or the second side surface. The central region has a first thickness, and the side region has a second thickness that is less than the first thickness.

公开(公告)号：US20200243126A1

公开(公告)日：2020-07-30

申请号：US16261617

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: G11C11/16 ,  G11C13/00

Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.

公开(公告)号：US10726896B1

公开(公告)日：2020-07-28

申请号：US16261617

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00

Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.

公开(公告)号：US10690845B1

公开(公告)日：2020-06-23

申请号：US16298354

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Abu Thomas ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/136 ,  H01L27/12 ,  G02B6/30

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to three dimensional (3D) optical interconnect structures and methods of manufacture. The structure includes: a first structure having a grating coupler and a first optical waveguide structure; and a second structure having a second optical waveguide structure in alignment with the first optical waveguide structure and which has a modal effective index that matches to the first optical waveguide structure.

公开(公告)号：US20200026000A1

公开(公告)日：2020-01-23

申请号：US16040896

申请日：2018-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136

Abstract: Structures including a waveguide arrangement and methods of fabricating a structure that includes a waveguide arrangement. A second waveguide spaced in a lateral direction from a first waveguide, a third waveguide spaced in a vertical direction from the first waveguide, and a fourth waveguide spaced in the vertical direction from the second waveguide. The third waveguide is arranged in the lateral direction to provide a first overlapping relationship with the first waveguide. The fourth waveguide is arranged in the lateral direction to provide a second overlapping relationship with the second waveguide.

公开(公告)号：US10468456B2

公开(公告)日：2019-11-05

申请号：US15898562

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.

公开(公告)号：US10468083B1

公开(公告)日：2019-11-05

申请号：US16010841

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G11C5/06 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01L43/12 ,  H01L43/10

Abstract: Integrated circuits and methods of operating and producing the same are provided. In an exemplary embodiment, an integrated circuit includes a look up table with a first and second memory cell. The first memory cell includes a first magneto electric (ME) layer, a first free layer adjacent to the first ME layer, and a first fixed layer. The second memory cell includes a second ME layer, a second free layer adjacent to the second ME layer, and a second fixed layer. A first word line is in direct communication with the first and second free layers, wherein direct communication is a connection through zero, one, or more intervening components that are electrical conductors. A first bit line is in direct communication with the first ME layer, and a second bit line is in direct communication with the second ME layer.