公开(公告)号：US07191375B2

公开(公告)日：2007-03-13

申请号：US10041040

申请日：2001-12-28

申请人： Gary Solomon ,  David Harriman ,  Jasmin Ajanovic

发明人： Gary Solomon ,  David Harriman ,  Jasmin Ajanovic

IPC分类号： H04L1/18

CPC分类号： H03M13/00 ,  H04L1/1685

摘要： A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet for a request transaction to a receiving device. The receiving device checks for error conditions. If an error condition exists and if the packet for the request transaction indicates that a completion is not expected by the transmitting device, an error message is delivered by the receiving device to the transmitting device.

摘要翻译： 发送装置和接收装置经由计算机系统内的高速串行接口耦合。 发送装置向接收装置发送用于请求事务的分组。 接收设备检查错误状况。 如果存在错误条件，并且如果请求事务的分组指示发送设备不期望完成，则接收设备将错误消息传递给发送设备。

公开(公告)号：US07184399B2

公开(公告)日：2007-02-27

申请号：US10040702

申请日：2001-12-28

申请人： David M. Lee ,  Kenneth C. Creta ,  Jasmin Ajanovic ,  Gary Solomon ,  David Harriman

发明人： David M. Lee ,  Kenneth C. Creta ,  Jasmin Ajanovic ,  Gary Solomon ,  David Harriman

IPC分类号： H04J1/16 ,  H04J3/14

CPC分类号： G06F13/4282 ,  G06F2213/0026

摘要： A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found then the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.

摘要翻译： 请求设备和完成设备经由计算机系统内的高速串行接口耦合。 请求设备向完成设备发送用于请求事务的分组。 完成设备在维护请求的过程中检查错误状况。 如果发现错误条件，则完成装置发送完成状态为成功以外的完成数据包。 完成分组包括完整的识别字段。 请求设备记录完成的识别值，并在寄存器中指示已经接收到完成分组具有不成功的完成状态。

公开(公告)号：US06993611B2

公开(公告)日：2006-01-31

申请号：US10655523

申请日：2003-09-03

申请人： Jasmin Ajanovic ,  David Harriman

发明人： Jasmin Ajanovic ,  David Harriman

IPC分类号： G06F13/40 ,  H04J3/16

CPC分类号： G06F13/124

摘要： A point-to-point interconnection and communication architecture, protocol and related methods. System resources are dynamically shared based on contents of information received for transmission within the system. Virtual channels may be used for transmission of the information received for transmission over a general input/output (GIO) bus.

摘要翻译： 一种点对点互连和通信架构，协议和相关方法。 系统资源是基于收到的用于在系统内传输的信息的内容动态共享的。 可以使用虚拟通道来传输通过一般输入/输出（GIO）总线传输的信息。

公开(公告)号：US06978351B2

公开(公告)日：2005-12-20

申请号：US10335424

申请日：2002-12-30

申请人： Randy B. Osborne ,  Kenneth C. Creta ,  Joseph A. Bennett ,  Jasmin Ajanovic

发明人： Randy B. Osborne ,  Kenneth C. Creta ,  Joseph A. Bennett ,  Jasmin Ajanovic

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F13/42

CPC分类号： G06F13/4243

摘要： To reduce prefetch overshoot when prefetching partial data sets along the path from input-output bus to system memory, a prefetch field is used to communicate the amount of data that a prefetching entity upstream may prefetch. Utilizing a prefetch field in such a manner reduces the fetching of unneeded data past the end of the requested data, resulting in overall increased system performance.

摘要翻译： 为了在沿着从输入 - 输出总线到系统存储器的路径预取部分数据集时减少预取过冲，使用预取字段来传送预取实体上游可能预取的数据量。 以这种方式利用预取字段减少了在所请求的数据的结尾之后提取不需要的数据，导致整体上提高的系统性能。

公开(公告)号：US06718512B2

公开(公告)日：2004-04-06

申请号：US10360339

申请日：2003-02-06

申请人： Randy B. Osborne ,  Jasmin Ajanovic

发明人： Randy B. Osborne ,  Jasmin Ajanovic

IPC分类号： G06F1100

CPC分类号： H04L1/0061 ,  H04L1/004 ,  H04L7/0083 ,  H04L7/048

摘要： A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

摘要翻译： 或者（b）在发送代理向接收代理发送的数据的传送期间检测同步错误的方法：（a）当发送代理在一个或多个时钟信号中对数据进行编码时，（a）用数据奇偶校验功能编码的数据奇偶校验， ）标题奇偶校验，当发送代理编码一个或多个时钟信号中的标题信息时，用标题奇偶校验功能编码。 当接收方：（a）被配置为接收数据奇偶校验并且实际接收到标题奇偶校验时，或者（b）被配置为接收标题奇偶校验并实际接收数据奇偶校验，则检测到同步错误状况。

公开(公告)号：US06587988B1

公开(公告)日：2003-07-01

申请号：US09469397

申请日：1999-12-22

申请人： Randy B. Osborne ,  Jasmin Ajanovic

发明人： Randy B. Osborne ,  Jasmin Ajanovic

IPC分类号： G06F1100

CPC分类号： H04L1/0061 ,  H04L1/004 ,  H04L7/0083 ,  H04L7/048

摘要： A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

公开(公告)号：US06272563B1

公开(公告)日：2001-08-07

申请号：US09186210

申请日：1998-11-03

申请人： Jasmin Ajanovic ,  David J. Harriman ,  C. Brendan S. Traw

发明人： Jasmin Ajanovic ,  David J. Harriman ,  C. Brendan S. Traw

IPC分类号： G06F1314

CPC分类号： H04L12/40058 ,  G06F13/4022 ,  G06F15/17381 ,  H04L12/40071 ,  H04Q2213/13093 ,  H04Q2213/13141 ,  H04Q2213/13216 ,  H04Q2213/13299

摘要： One embodiment of an apparatus for communicating routing and attribute information for a transaction between hubs in a computer system is disclosed. The apparatus includes a data path input/output unit to output a packet header for a transaction. The packet header includes a transaction descriptor routing field to identify an initiating agent that initiated the transaction. The transaction descriptor routing field includes a hub identification portion and a pipe identification portion. The hub identification portion identifies a hub that contains the initiating agent. The pipe identification portion further identifies the initiating agent within the identified hub if the transaction has no ordering requirements with respect to a second agent in the identified hub.

摘要翻译： 公开了一种用于在计算机系统中的集线器之间传送用于事务的路由和属性信息的装置的一个实施例。 该装置包括用于输出交易的分组报头的数据路径输入/输出单元。 分组报头包括事务描述符路由字段以标识发起事务的启动代理。 事务描述符路由字段包括集线器识别部分和管道识别部分。 集线器识别部分标识包含启动代理的集线器。 如果事务对于所识别的集线器中的第二代理没有排序要求，则管道识别部分进一步识别所识别的集线器内的启动代理。

公开(公告)号：US06253270B1

公开(公告)日：2001-06-26

申请号：US09223045

申请日：1998-12-30

申请人： Jasmin Ajanovic ,  David J. Harriman

发明人： Jasmin Ajanovic ,  David J. Harriman

IPC分类号： G06F1336

CPC分类号： G06F13/36

摘要： An apparatus for arbitrating ownership of an interface between two hub agents is described. The apparatus includes a data path input/output unit to communicate with a data path and an arbitration circuit. The arbitration unit includes a least recently serviced status tracking circuit to determine which of the data path input/output unit and a device that transmits the second request signal has been granted ownership of the data path least recently, an arbitration signal output circuit to output a first request signal, and an arbitration signal input circuit to receive a second request signal. The arbitration unit grants ownership of the data path to the data path input/output unit when the first request signal is asserted if the second request signal is not asserted.

摘要翻译： 描述了用于仲裁两个集线器代理之间的接口的所有权的装置。 该装置包括与数据路径和仲裁电路通信的数据路径输入/输出单元。 仲裁单元包括最近最少服务的状态跟踪电路，用于确定数据路径输入/输出单元中的哪一个以及发送第二请求信号的设备最近被授予数据路径的所有权，仲裁信号输出电路输出 第一请求信号和仲裁信号输入电路，以接收第二请求信号。 如果第二请求信号未被断言，当第一请求信号被断言时，仲裁单元将数据路径的所有权授予数据路径输入/输出单元。

公开(公告)号：US6088772A

公开(公告)日：2000-07-11

申请号：US874415

申请日：1997-06-13

申请人： David J. Harriman ,  Brian K. Langendorf ,  Jasmin Ajanovic

发明人： David J. Harriman ,  Brian K. Langendorf ,  Jasmin Ajanovic

IPC分类号： G06F13/16 ,  G06F13/18

CPC分类号： G06F13/1631

摘要： A method and apparatus for ordering memory access commands. A command ordering circuit which is described includes a plurality of command slots which receive memory access commands. A page register stores a value indicating a last page accessed by a prior memory access command. Comparators compare the value in the page register to values stored in the command slots, and an arbiter receives outputs from the comparators and selects a command from one of the slots. According to the method described, memory accesses are reordered depending on the portion of memory accessed. A first memory access command requesting access to a first portion of memory is issued. Additional memory access commands also referencing the first portion of memory are issued until a count is reached. After the count is reached, a second memory access command which references a second portion of memory is issued.

摘要翻译： 一种用于排序存储器访问命令的方法和装置。 所描述的命令排序电路包括接收存储器访问命令的多个命令槽。 页面寄存器存储指示由先前存储器访问命令访问的最后页面的值。 比较器将页寄存器中的值与存储在命令槽中的值进行比较，仲裁器从比较器接收输出，并从其中一个插槽中选择一个命令。 根据所描述的方法，存储器访问根据访问的存储器的部分重新排序。 发出请求访问存储器的第一部分的第一存储器访问命令。 还会引用额外的存储器访问命令，同时引用存储器的第一部分直到达到计数。 在达到计数之后，发出引用存储器的第二部分的第二存储器访问命令。

公开(公告)号：US5859988A

公开(公告)日：1999-01-12

申请号：US536275

申请日：1995-09-29

申请人： Jasmin Ajanovic ,  Patrick N. Kearns

发明人： Jasmin Ajanovic ,  Patrick N. Kearns

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4059 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A bridge coupling a primary bus to two secondary buses. The bridge contains three interfaces, one for the primary bus and the other two for the two secondary buses. Control circuitry is included within the bridge to support the execution of a transaction initiated by a bus master upstream of the bridge to a target downstream of the bridge. The bridge also supports the execution of a transaction initiated by a bus master coupled to either one of the secondary buses to a target upstream of the bridge.

摘要翻译： 将主母线耦合到两条辅助母线的桥。 该桥包含三个接口，一个用于主要总线，另外两个用于两条辅助总线。 控制电路被包括在桥内，以支持由桥接器上游的总线主机发起的事务执行到网桥下游的目标。 桥接器还支持由耦合到任一个辅助总线的总线主机发起的交易到达桥上游的目标。