公开(公告)号：US06574777B2

公开(公告)日：2003-06-03

申请号：US10023789

申请日：2001-12-17

申请人： Randy B. Osborne ,  Jasmin Ajanovic

发明人： Randy B. Osborne ,  Jasmin Ajanovic

IPC分类号： G11B2700

CPC分类号： H04L1/0061 ,  H04L1/004 ,  H04L7/0083 ,  H04L7/048

摘要： A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

公开(公告)号：US06978351B2

公开(公告)日：2005-12-20

申请号：US10335424

申请日：2002-12-30

申请人： Randy B. Osborne ,  Kenneth C. Creta ,  Joseph A. Bennett ,  Jasmin Ajanovic

发明人： Randy B. Osborne ,  Kenneth C. Creta ,  Joseph A. Bennett ,  Jasmin Ajanovic

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F13/42

CPC分类号： G06F13/4243

摘要： To reduce prefetch overshoot when prefetching partial data sets along the path from input-output bus to system memory, a prefetch field is used to communicate the amount of data that a prefetching entity upstream may prefetch. Utilizing a prefetch field in such a manner reduces the fetching of unneeded data past the end of the requested data, resulting in overall increased system performance.

摘要翻译： 为了在沿着从输入 - 输出总线到系统存储器的路径预取部分数据集时减少预取过冲，使用预取字段来传送预取实体上游可能预取的数据量。 以这种方式利用预取字段减少了在所请求的数据的结尾之后提取不需要的数据，导致整体上提高的系统性能。

公开(公告)号：US06718512B2

公开(公告)日：2004-04-06

申请号：US10360339

申请日：2003-02-06

申请人： Randy B. Osborne ,  Jasmin Ajanovic

发明人： Randy B. Osborne ,  Jasmin Ajanovic

IPC分类号： G06F1100

CPC分类号： H04L1/0061 ,  H04L1/004 ,  H04L7/0083 ,  H04L7/048

摘要： A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

摘要翻译： 或者（b）在发送代理向接收代理发送的数据的传送期间检测同步错误的方法：（a）当发送代理在一个或多个时钟信号中对数据进行编码时，（a）用数据奇偶校验功能编码的数据奇偶校验， ）标题奇偶校验，当发送代理编码一个或多个时钟信号中的标题信息时，用标题奇偶校验功能编码。 当接收方：（a）被配置为接收数据奇偶校验并且实际接收到标题奇偶校验时，或者（b）被配置为接收标题奇偶校验并实际接收数据奇偶校验，则检测到同步错误状况。

公开(公告)号：US06587988B1

公开(公告)日：2003-07-01

申请号：US09469397

申请日：1999-12-22

申请人： Randy B. Osborne ,  Jasmin Ajanovic

发明人： Randy B. Osborne ,  Jasmin Ajanovic

IPC分类号： G06F1100

CPC分类号： H04L1/0061 ,  H04L1/004 ,  H04L7/0083 ,  H04L7/048

摘要： A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

公开(公告)号：US09087603B2

公开(公告)日：2015-07-21

申请号：US12369105

申请日：2009-02-11

申请人： Randy B. Osborne

发明人： Randy B. Osborne

IPC分类号： G11C8/00 ,  G11C11/4094 ,  G11C7/10 ,  G11C8/18

CPC分类号： G11C11/4094 ,  G11C7/1012 ,  G11C8/18

摘要： Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed.

公开(公告)号：US07673111B2

公开(公告)日：2010-03-02

申请号：US11318028

申请日：2005-12-23

申请人： Shelley Chen ,  Randy B. Osborne

发明人： Shelley Chen ,  Randy B. Osborne

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/1642 ,  Y02D10/14

摘要： In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in response thereto to select a first or a second mode for the scheduling circuitry, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules consolidated commands to represent more than one separate single command. Other embodiments are described.

摘要翻译： 在一些实施例中，芯片包括包括写入请求的请求队列，以及调度电路来调度包括响应于写入请求的命令的命令。 芯片还包括模式选择电路，用于监视请求队列并响应于此选择用于调度电路的第一或第二模式，其中在第一模式中，调度电路将某些命令调度为单独的单个命令，并且在第二模式中 调度电路安排统一的命令来表示多个独立的单个命令。 描述其他实施例。

公开(公告)号：US07167946B2

公开(公告)日：2007-01-23

申请号：US10676882

申请日：2003-09-30

申请人： Randy B. Osborne

发明人： Randy B. Osborne

IPC分类号： G06F12/00

CPC分类号： G11C11/4094 ,  G11C11/4076

摘要： Apparatus and method to implicitly transmit a command to close a row of memory cells within a memory device as part of the transmission of an activate command to open another row of memory cells within the memory device.

摘要翻译： 用于隐藏地发送命令以关闭存储器设备内的一行存储器单元的装置和方法，作为激活命令的传输的一部分，以打开存储器设备内的另一行存储器单元。

公开(公告)号：US06983356B2

公开(公告)日：2006-01-03

申请号：US10325795

申请日：2002-12-19

申请人： Hemant G. Rotithor ,  Randy B. Osborne ,  Donald W. McCauley

发明人： Hemant G. Rotithor ,  Randy B. Osborne ,  Donald W. McCauley

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0215 ,  G06F2212/502 ,  G06F2212/6022

摘要： A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level. Prefetches are inserted conservatively if the memory bandwidth utilization (MBU) rate is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.

摘要翻译： 从存储器件预取的方法包括确定预取缓冲器命中率（PBHR）和存储器带宽利用率（MBU）速率。 如果存储器带宽占用率（MBU）高于MBU阈值级别，并且预取缓冲区命中率（PBHR）高于PBHR阈值级别，则会大大插入预取。 如果存储器带宽占用率（MBU）高于MBU阈值级别，并且预取缓冲区命中率（PBHR）低于PBHR阈值级别，则保留预存取值。

公开(公告)号：US06941425B2

公开(公告)日：2005-09-06

申请号：US10010994

申请日：2001-11-12

申请人： Randy B. Osborne

发明人： Randy B. Osborne

IPC分类号： G06F13/16 ,  G06F13/00

CPC分类号： G06F13/1626 ,  G06F13/161

摘要： A method and apparatus for the optimization of memory read operations via read launch optimizations in memory interconnect are disclosed. In one embodiment, a write request may be preempted by a read request.

摘要翻译： 公开了一种通过存储器互连中的读取启动优化优化存储器读取操作的方法和装置。 在一个实施例中，写请求可以被读请求抢占。

公开(公告)号：US6008813A

公开(公告)日：1999-12-28

申请号：US905238

申请日：1997-08-01

申请人： Hugh C. Lauer ,  Randy B. Osborne ,  Hanspeter Pfister

发明人： Hugh C. Lauer ,  Randy B. Osborne ,  Hanspeter Pfister

IPC分类号： G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/08 ,  G06T15/40

CPC分类号： G06T15/08 ,  G06T1/60 ,  G06T15/005 ,  G06T15/40

摘要： Apparatus is provided to enable real-time volume rendering on a personal computer or a desktop computer in which a technique involving blocking of voxel data organizes the data so that all voxels within a block are stored at consecutive memory addresses within a single memory model, making possible fetching an entire block of data in a burst rather than one voxel at a time. This permits utilization of DRAM memory modules which provide high capacity and low cost with substantial space savings. Additional techniques including sectioning reduces the amount of intermediate storage in a processing pipeline to an acceptable level for semiconductor implementation. A multiplexing technique takes advantage of blocking to reduce the amount of data needed to be transmitted per block, thus reducing the number of pins and the rates at which data must be transmitted across the pins connecting adjacent processing modules with each other. A mini-blocking technique saves the time needed to process sections by avoiding reading entire blocks for voxels near the boundary between a section and previously processed sections.

摘要翻译： 提供了一种用于在个人计算机或台式计算机上实时体积渲染的装置，其中涉及阻塞体素数据的技术组织数据，使得块内的所有体素被存储在单个存储器模型内的连续存储器地址处，使得 一次可能在突发而不是一个体素中获取整个数据块。 这允许利用提供高容量和低成本的DRAM存储器模块，同时节省了大量空间。 包括切片的其他技术将处理管线中的中间存储量减少到半导体实现的可接受水平。 复用技术利用阻塞来减少每个块需要传输的数据量，从而减少引脚数量和数据必须在连接相邻处理模块的引脚之间传输的速率。 微型阻塞技术通过避免读取部分和先前处理的部分之间边界附近的体素的整个块来节省处理部分所需的时间。