公开(公告)号：US20230197777A1

公开(公告)日：2023-06-22

申请号：US17556748

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Cheng-Ying Huang ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Patrick Morrow ,  Ashish Agrawal ,  Willy Rachmady ,  Nazila Haratipour ,  Seung Hoon Sung ,  I-Cheng Tung ,  Christopher M. Neumann ,  Koustav Ganguly ,  Subrina Rafique

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices utilizing a metal fill in an epi region of a stacked transistor configuration. In one example, an n-channel device and the p-channel device may both be GAA transistors each having any number of nanoribbons extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. A metal fill may be provided around the source or drain region of the bottom semiconductor device to provide a high contact area between the highly conductive metal fill and the epitaxial material of that source or drain region. Metal fill may also be used around the top source or drain region to further improve conductivity throughout both of the stacked source or drain regions.

公开(公告)号：US11677017B2

公开(公告)日：2023-06-13

申请号：US17472015

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/15 ,  H01L29/78 ,  H01L29/82 ,  H01L29/43

CPC classification number: H01L29/66977 ,  G06N10/00 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/158 ,  H01L29/66984 ,  H01L29/7831 ,  H01L29/82 ,  H01L29/437

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US11664421B2

公开(公告)日：2023-05-30

申请号：US16987874

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Jeanette M. Roberts ,  Nicole K. Thomas ,  James S. Clarke

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76 ,  H01L29/165 ,  H01L29/12 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/16 ,  G06N10/00 ,  H01L29/82

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  G06N10/00 ,  H01L29/1054 ,  H01L29/127 ,  H01L29/16 ,  H01L29/165 ,  H01L29/423 ,  H01L29/42376 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/7782 ,  H01L29/778 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material disposed above the quantum well stack, wherein the insulating material includes a trench; and a gate metal disposed on the insulating material and extending into the trench.

公开(公告)号：US11658212B2

公开(公告)日：2023-05-23

申请号：US16274572

申请日：2019-02-13

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Stephanie A. Bojarski ,  Roman Caudillo ,  David J. Michalak ,  Jeanette M. Roberts ,  Thomas Francis Watson

IPC: H01L29/12 ,  H01L29/16 ,  G06N10/00 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L29/122 ,  G06N10/00 ,  H01L29/16 ,  H01L29/7851 ,  H01L23/5226

Abstract: Disclosed herein are quantum dot devices with conductive liners, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base, a first fin extending from the base, a second fin extending from the base, a conductive material between the first fin and the second fin, and a dielectric material between the conductive material and the first fin.

公开(公告)号：US11557630B2

公开(公告)日：2023-01-17

申请号：US16643322

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Nicole K. Thomas ,  Abhishek A. Sharma ,  Hubert C. George ,  Jeanette M. Roberts ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Kanwaljit Singh ,  James S. Clarke

IPC: H01L27/24 ,  H01L45/00 ,  G06N10/00 ,  H01L29/12 ,  H01L29/15 ,  H01L29/43 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423

Abstract: Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.

公开(公告)号：US11482614B2

公开(公告)日：2022-10-25

申请号：US16645962

申请日：2017-12-23

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Willy Rachmady ,  Kanwaljit Singh ,  Nicole K. Thomas ,  Hubert C. George ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Payam Amin ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/66 ,  G06N10/00 ,  H01L27/088 ,  H01L29/12 ,  H01L29/165 ,  H01L29/423 ,  H01L29/43 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.

公开(公告)号：US11158731B2

公开(公告)日：2021-10-26

申请号：US16642886

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/15 ,  H01L29/78 ,  H01L29/82 ,  H01L29/43

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US20210296480A1

公开(公告)日：2021-09-23

申请号：US17341559

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Nicole K. Thomas ,  Zachary R. Yoscovits ,  Hubert C. George ,  Jeanette M. Roberts ,  Ravi Pillarisetty

IPC: H01L29/775 ,  H01L29/66 ,  G06N10/00 ,  H01L29/12

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

公开(公告)号：US20200350423A1

公开(公告)日：2020-11-05

申请号：US16642886

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  H01L29/82 ,  H01L29/78 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/15 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US20200321436A1

公开(公告)日：2020-10-08

申请号：US16650299

申请日：2017-12-23

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Kanwaljit Singh ,  Roza Kotlyar ,  Patrick H. Keys ,  James S. Clarke

IPC: H01L29/15 ,  G06N10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.