公开(公告)号：US10461248B2

公开(公告)日：2019-10-29

申请号：US15997904

申请日：2018-06-05

Applicant: International Business Machines Corporation

Inventor： Prasad Bhosale ,  Raghuveer R. Patlolla ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08

Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.

公开(公告)号：US20190304929A1

公开(公告)日：2019-10-03

申请号：US15938207

申请日：2018-03-28

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Baozhen Li ,  Xiao Hu Liu ,  Griselda Bonilla

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for fabricating the structure is described.

公开(公告)号：US20190304928A1

公开(公告)日：2019-10-03

申请号：US15938155

申请日：2018-03-28

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Baozhen Li ,  Xiao Hu Liu ,  Griselda Bonilla

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.

公开(公告)号：US20190280080A1

公开(公告)日：2019-09-12

申请号：US16419619

申请日：2019-05-22

Applicant: International Business Machines Corporation

Inventor： Baozhen Li ,  Kirk Peterson ,  John Sheets ,  Lawrence A. Clevenger ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L49/02 ,  H01L21/48 ,  H01L23/522

Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.

公开(公告)号：US20190273204A1

公开(公告)日：2019-09-05

申请号：US16414336

申请日：2019-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Liying Jiang ,  Sebastian Naczas ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method of forming magnetic device structures and electrical contacts, including removing a portion of a second interlayer dielectric (ILD) layer to expose an underlying portion of a cap layer in a first device region, wherein the cap layer is on a first ILD layer, while leaving an ILD block in a second device region, forming a spacer layer on the exposed portion of the cap layer in the first device region, forming an electrical contact layer on the spacer layer in the first device region, forming a magnetic device layer on the electrical contact layer and ILD block, removing portions of the magnetic device layer to form a magnetic device stack on the ILD block, and removing portions of the electrical contact layer to form electrical contact pillars, wherein the portions of the electrical contact layer and portions of the magnetic device layer are removed at the same time.

公开(公告)号：US10381263B1

公开(公告)日：2019-08-13

申请号：US15971783

申请日：2018-05-04

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Theodorus E Standaert

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/311

Abstract: A first dielectric layer on a substrate is provided. The first dielectric layer has a first level metal line embedded in the dielectric. An opposite gouging feature is created in a top surface of the first level metal line. The opposite gouging feature has a protuberant shape relative to the first level metal line. A second dielectric layer is formed over the first dielectric layer. A compound recess is formed in the second dielectric layer. A first portion of the recess is for a via connector positioned over the opposite gouging feature. A second portion of the recess for a second level metal line. In another aspect of the invention, a device is produced using the method.

公开(公告)号：US20190237340A1

公开(公告)日：2019-08-01

申请号：US16377975

申请日：2019-04-08

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/32134 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/32136 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2221/1036

Abstract: An interconnect dielectric material having an opening formed therein is first provided. A surface nitridation process is then performed to form a nitridized dielectric surface layer within the interconnect dielectric material. A metal layer is formed on the nitridized dielectric surface layer and then an anneal is performed to form a metal nitride layer between the metal layer and the nitridized dielectric surface layer. A portion of the originally deposited metal layer that is not reacted with the nitridized dielectric surface is then selectively removed and thereafter an electrical conducting structure is formed directly on the metal nitride layer that is present in the opening.

公开(公告)号：US10361265B2

公开(公告)日：2019-07-23

申请号：US15816622

申请日：2017-11-17

Applicant: International Business Machines Corporation

Inventor： Baozhen Li ,  Kirk Peterson ,  John Sheets ,  Lawrence A. Clevenger ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/48

Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.

公开(公告)号：US20190207109A1

公开(公告)日：2019-07-04

申请号：US15861158

申请日：2018-01-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Chih-Chao Yang ,  Lawrence A. Clevenger

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Embodiments of the invention are directed to a resistive switching device (RSD) that includes a first terminal, a second terminal, an active region having a switchable conduction state, and a protuberant contact communicatively coupled to the first terminal. The protuberant contact is configured to communicatively couple the first terminal through a first barrier liner to a first electrode line of a crossbar array. In embodiments of the invention, the protuberant contact is positioned with respect to the first barrier liner such that the first barrier liner does not impacting the switchable conduction state of the active region. In embodiments of the invention, the protuberant contact is positioned with respect to the first barrier liner such that the first barrier liner does not directly contact the first terminal.

公开(公告)号：US10332955B2

公开(公告)日：2019-06-25

申请号：US15816531

申请日：2017-11-17

Applicant: International Business Machines Corporation

Inventor： Baozhen Li ,  Kirk Peterson ,  John Sheets ,  Lawrence A. Clevenger ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/48

Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.