公开(公告)号：US20200035620A1

公开(公告)日：2020-01-30

申请号：US16594297

申请日：2019-10-07

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Baozhen Li ,  Xiao Hu Liu ,  Griselda Bonilla

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level.

公开(公告)号：US11295982B2

公开(公告)日：2022-04-05

申请号：US16437742

申请日：2019-06-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Katsuyuki Sakuma ,  Huan Hu ,  Xiao Hu Liu

IPC: H01L21/78 ,  H01L23/31 ,  H01L21/3065 ,  H01L21/56 ,  H01L21/683

Abstract: A method of fabricating ultra-thin chips is provided. The method includes patterning circuit elements onto a substrate such that sections of the substrate are exposed and etching trenches into the sections of the substrate to define pedestals respectively associated with a corresponding circuit element. The method further includes depositing stressor layer material onto the circuit elements and applying handling tape to the stressor layer material. In addition, the method includes at least one of weakening the substrate in a plane defined by base corners of the pedestals and initiating substrate cracking at the base corners of the pedestals to encourage spalling of the pedestals off the substrate.

公开(公告)号：US20210183773A1

公开(公告)日：2021-06-17

申请号：US16712231

申请日：2019-12-12

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Arvind Kumar ,  Lawrence A. Clevenger ,  Steven Lorenz Wright ,  Wiren Dale Becker ,  Xiao Hu Liu

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.

公开(公告)号：US11015913B2

公开(公告)日：2021-05-25

申请号：US16390255

申请日：2019-04-22

Applicant: International Business Machines Corporation

Inventor： Huan Hu ,  Ning Li ,  Xiao Hu Liu ,  Katsuyuki Sakuma

IPC: B81B3/00 ,  B81C1/00 ,  G01B7/16 ,  G01L1/22

Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.

公开(公告)号：US10475753B2

公开(公告)日：2019-11-12

申请号：US15938155

申请日：2018-03-28

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Baozhen Li ,  Xiao Hu Liu ,  Griselda Bonilla

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.

公开(公告)号：US20180331028A1

公开(公告)日：2018-11-15

申请号：US15595141

申请日：2017-05-15

Applicant: International Business Machines Corporation

Inventor： Charles E. Cox ,  Harald Huels ,  Arvind Kumar ,  Xiao Hu Liu ,  Ahmet S. Ozcan ,  Winfried W. Wilcke

IPC: H01L23/50 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L23/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16235

Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-hole vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

公开(公告)号：US09812359B2

公开(公告)日：2017-11-07

申请号：US14733445

申请日：2015-06-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Mukta G. Farooq ,  Carole D. Graas ,  Xiao Hu Liu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481

Abstract: Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.

公开(公告)号：US09670061B1

公开(公告)日：2017-06-06

申请号：US15262912

申请日：2016-09-12

Applicant: International Business Machines Corporation

Inventor： Huan Hu ,  Ning Li ,  Xiao Hu Liu ,  Katsuyuki Sakuma

IPC: H01L21/762 ,  B81B3/00 ,  B81C1/00

CPC classification number: G01B7/20 ,  B81B3/0097 ,  B81B2201/0214 ,  B81B2207/07 ,  B81C1/0038 ,  B81C2201/0194 ,  G01L1/2293

Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.

公开(公告)号：US20140302685A1

公开(公告)日：2014-10-09

申请号：US14307960

申请日：2014-06-18

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Griselda Bonilla ,  Xiao Hu Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Hosadurga K. Shobha ,  Daewon Yang

IPC: H01L21/02

CPC classification number: H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

Abstract: A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g., greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example, copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

Abstract translation: 公开了介电盖和相关方法。 在一个实施例中，电介质盖包括具有光学带隙（例如，大于约3.0电子伏特）的电介质材料，以在固化处理期间基本上阻挡紫外线辐射，并且包括氮与电子给体，双键电子。 介电盖表现出高模量，并且在用于例如铜低k后端（BEOL）纳米电子器件的ULK UV固化处理之下是稳定的，导致更少的膜和器件开裂以及改进的可靠性。

公开(公告)号：US10964881B2

公开(公告)日：2021-03-30

申请号：US15825171

申请日：2017-11-29

Applicant: International Business Machines Corporation

Inventor： Bruce G. Elmegreen ,  Marcelo A. Kuroda ,  Xiao Hu Liu ,  Glenn J. Martyna ,  Dennis M. Newns ,  Paul M. Solomon

IPC: H01L41/09

Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.