公开(公告)号：US20240119000A1

公开(公告)日：2024-04-11

申请号：US17962829

申请日：2022-10-10

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Matthias Klein ,  Sascha Junghans ,  Kevin Lopes

IPC: G06F12/0802 ,  G06F13/16

CPC classification number: G06F12/0802 ,  G06F13/1668 ,  G06F2212/621

Abstract: A data processing system includes a system fabric coupling a coherence manager and an input/output (I/O) requestor. The I/O requestor issues a first snoop request of a first I/O store operation and a subsequent second snoop request of a second I/O store operation. Each of the first and second snoop requests specifies an update to a respective storage location identified by a coherent memory address. The I/O requestor receives respective ownership coherence responses for each of the first and second I/O store operations. The respective first and second ownership coherence responses indicate the coherence manager has concurrent coherence ownership of the memory address for both the first and second I/O store operations. In response to receipt of each of the ownership coherence responses, the I/O requestor issues respective first and second execute coherence responses to command the coherence manager to initiate updates to the respective storage locations.

公开(公告)号：US20230318979A1

公开(公告)日：2023-10-05

申请号：US17708073

申请日：2022-03-30

Applicant: International Business Machines Corporation

Inventor： Avery Francois ,  Kenneth Douglas Klapproth ,  Guy G. Tracy ,  Matthias Klein ,  Gregory William Alexander

IPC: H04L47/10 ,  H04L45/122

CPC classification number: H04L47/13 ,  H04L45/122

Abstract: Embodiments include processing commands on multiprocessor chip having a plurality of nodes that are interconnected via a clockwise ring network and a counterclockwise ring network. Aspects include receiving a command for execution and based at least in part on a determination that the clockwise ring network and the counterclockwise ring network are both available for transmission, performing a bidirectional execution of the command. The bidirectional execution includes transmitting a first warning signal on the clockwise ring network and a second warning signal on the counterclockwise ring network, transmitting the command on the clockwise ring network a first number of clock cycles after the first warning signal, and transmitting the command on the counterclockwise ring network a second number of clock cycles after the second warning signal.

公开(公告)号：US11762659B2

公开(公告)日：2023-09-19

申请号：US17480337

申请日：2021-09-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Brenton Belmar ,  Peter Dana Driever

IPC: G06F9/30 ,  G06F9/451 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/54 ,  G06F11/07

CPC classification number: G06F9/30043 ,  G06F9/30145 ,  G06F9/3871 ,  G06F9/4411 ,  G06F9/451 ,  G06F9/544 ,  G06F9/546 ,  G06F11/0772

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

公开(公告)号：US11449367B2

公开(公告)日：2022-09-20

申请号：US16286987

申请日：2019-02-27

Applicant: International Business Machines Corporation

Inventor： Matthias Klein ,  Simon Weishaupt ,  Anthony Thomas Sofia ,  Jonathan D. Bradbury ,  Mark S. Farrell ,  Mahmoud Amin ,  Timothy Slegel

IPC: G06F9/52 ,  G06F9/48

Abstract: A method is provided that includes receiving, by a firmware from an originating software, an asynchronous request for an instruction of an algorithm for compression of data. The firmware operates on a first processor and the originating software operates on a second processor. The firmware issues a synchronous request to the first processor to cause the processor to execute the instruction synchronously. It is determined, by the firmware, whether an interrupt is received from the first processor with respect to the first processor executing the instruction. The firmware retries the issuance of the synchronous request each time the interrupt is received until a retry threshold is reached.

公开(公告)号：US11321146B2

公开(公告)日：2022-05-03

申请号：US16407819

申请日：2019-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ralf Winkelmann ,  Michael Fee ,  Matthias Klein ,  Carsten Otte ,  Edward W. Chencinski ,  Hanno Eichelberger

IPC: G06F9/46 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0842 ,  G06F9/54

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

公开(公告)号：US11314555B2

公开(公告)日：2022-04-26

申请号：US16550829

申请日：2019-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Matthias Klein ,  Timothy Siegel ,  Anthony T. Sofia ,  Simon Weishaupt ,  Bruce C. Giamei ,  Louis P. Gomes ,  Mahmoud Amin

IPC: G06F9/50 ,  H03M7/30 ,  G06F9/52

Abstract: A processor requests that a data transformation operation be performed using another processor, in which the data transformation operation is performed asynchronously. A determination is made that the data transformation operation performed using the other processor has completed unsatisfactorily, and based on the unsatisfactory completion, status relating to performance of the data transformation operation is incomplete. The data transformation operation is then re-executed synchronously using the one processor, and the re-executing provides status information unavailable in performing the data transformation operation asynchronously.

公开(公告)号：US11249776B2

公开(公告)日：2022-02-15

申请号：US16789519

申请日：2020-02-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marco Kraemer ,  Christoph Raisch ,  Bernd Nerz ,  Donald William Schmidt ,  Matthias Klein ,  Sascha Junghans ,  Peter Dana Driever

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

公开(公告)号：US20220012159A1

公开(公告)日：2022-01-13

申请号：US16922223

申请日：2020-07-07

Applicant: International Business Machines Corporation

Inventor： Arun Joseph ,  Wolfgang Roesner ,  Anthony Saporito ,  Matthias Klein ,  SAMPATH GOUD BADDAM ,  Shashidhar Reddy

IPC: G06F11/36 ,  G06F9/30 ,  G06F30/20

Abstract: A method for collaborative logic designing and debugging of a circuit includes initiating, via a session manager, a hardware debug session that includes a plurality of instances of client applications that can access one or more source-codes associated with a logic design of the circuit, the plurality of instances of client applications configured to replicate an execution state of the logic design. The method also includes analyzing, using an instance of a first client application from the plurality of instances of client applications, a defect in the logic design based on the execution state of the logic design. The method also includes editing, using an instance of a second client application from the plurality of instances of client applications, the one or more source-codes, to repair the defect in the logic design.

公开(公告)号：US20210255999A1

公开(公告)日：2021-08-19

申请号：US16793113

申请日：2020-02-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Matthias Klein ,  Damir Anthony Jamsek ,  Bulent Abali ,  Ashutosh Misra ,  Preetham M. Lobo

IPC: G06F16/21 ,  G06F16/22

Abstract: Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.

公开(公告)号：US11010210B2

公开(公告)日：2021-05-18

申请号：US16527424

申请日：2019-07-31

Applicant: International Business Machines Corporation

Inventor： Robert J. Sonnelitter, III ,  Michael Fee ,  Craig R. Walters ,  Arthur O'Neill ,  Matthias Klein

IPC: G06F9/52 ,  G06F9/48 ,  G06F12/0802 ,  G06F9/54 ,  G06F9/38

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.