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    MMIO addressing using a translation lookaside buffer
    3.
    发明授权
    MMIO addressing using a translation lookaside buffer 有权

    公开(公告)号：US11321240B2

    公开(公告)日：2022-05-03

    申请号：US16003808

    申请日：2018-06-08

    Applicant: International Business Machines Corporation

    Inventor： Christoph Raisch ,  Marco Kraemer ,  Carsten Otte ,  Jonathan D. Bradbury ,  David Craddock

    IPC: G06F12/00 ,  G06F12/1027 ,  G06F13/16

    Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space that maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and generates, based on the determination, a first translation of the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address resulting from the translation is assigned to a device accessible via the identified bus. The method generates an entry in a translation lookaside buffer. A request directed to the device is sent via the identified bus to the bus address resulting from the translation.

    Simulating a system of computing systems
    5.
    发明授权
    Simulating a system of computing systems 有权

    公开(公告)号：US11444843B2

    公开(公告)日：2022-09-13

    申请号：US16701204

    申请日：2019-12-03

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Carsten Otte ,  Georg Drache ,  Joachim von Buttlar ,  Jens Mehler ,  Sebastian Stork

    IPC: H04L41/14

    Abstract: A computer-implemented method for simulating a system of at least two computing systems connected via at least one data packet connection, wherein a computing system comprises interconnect adapters for physical connections based on a physical layer protocol each. A packet switching component is provided, as are physical attachments for each interconnect adapter. The physical attachments are registered. A connection director is provided for managing the data packet exchange. In response to the receipt of a simulation start indicator, each physical attachment registers its unique address at the package switching component. This assigns unique identifiers for each computing system, and unique identifiers for simulated physical layer protocols.

    Memory access based I/O operations
    6.
    发明授权
    Memory access based I/O operations 有权

    公开(公告)号：US10901910B2

    公开(公告)日：2021-01-26

    申请号：US15946079

    申请日：2018-04-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Christoph Raisch ,  Carsten Otte ,  Matthias Brachmann ,  Marco Kraemer

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/1009 ,  G06F3/06 ,  G06F11/10

    Abstract: The invention relates to a method for transferring data between a computer program executed by a processor and an input/output device using a memory accessible by the computer program and the input/output device. An operating system provides a trigger address range in a virtual address space assigned to the computer program. A page fault is caused by accessing the trigger address by the computer program. A page fault handler handling the page fault acquires information for identifying the data to be transferred using the trigger address. The acquired information is provided to the input/output device and the identified data is transferred between the memory and the input/output device.

    Firmware or hardware component assist for memory mapped I/O
    7.
    发明授权
    Firmware or hardware component assist for memory mapped I/O 有权

    公开(公告)号：US10606759B2

    公开(公告)日：2020-03-31

    申请号：US15407621

    申请日：2017-01-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Marco Kraemer ,  Carsten Otte ,  Christoph Raisch

    IPC: G06F12/10 ,  G06F12/1009 ,  G06F3/06 ,  G06F12/1027

    Abstract: A method is provided for providing access to a data block in a device of a processing system. The device is connected to a processor of the processing system via an extension bus, and the processing system includes a memory connected to the processor via a memory bus, an operating system and hardware and/or firmware components for controlling access to the device. The method includes adding by the operating system for the data block a first entry in a page table of the processing system. The added entry represents the data block. A memory management unit (MMU) of the processing system may receive a request of the data block. Upon receiving the request, the MMU may instruct one of the hardware or firmware components to provide access to the data block using the added entry.

    Asymmetric storage data distribution
    8.
    发明授权
    Asymmetric storage data distribution 有权

    公开(公告)号：US10545681B2

    公开(公告)日：2020-01-28

    申请号：US15017688

    申请日：2016-02-08

    Applicant: International Business Machines Corporation

    Inventor： Marco Kraemer ,  Carsten Otte ,  Christoph Raisch

    IPC: G06F3/06

    Abstract: Aspects include defining a first percentage of storage areas in an array of multiple persistent storage elements as hot storage areas and a second percentage of storage areas as spare storage areas such that remaining storage areas define a third percentage as cold storage areas. Each of the storage areas are assigned to either the hot group, the spare group or the cold group, respectively. A hot and cold storage area each include a first storage block on two different storage elements, and the hot storage area and the cold storage area each include a corresponding second storage block on a storage element different to the storage element on which the first respective storage block is stored. The storage blocks are distributed across the storage elements such that blocks of storage areas with the highest write rate of all storage areas are placed on a hottest storage element.

    MEMORY MANAGEMENT UNIT AND METHOD FOR ACCESSING DATA
    10.
    发明申请
    MEMORY MANAGEMENT UNIT AND METHOD FOR ACCESSING DATA 有权
    存储器管理单元和访问数据的方法

    公开(公告)号：US20170046276A1

    公开(公告)日：2017-02-16

    申请号：US14824107

    申请日：2015-08-12

    Applicant: International Business Machines Corporation

    Inventor： Matthias Klein ,  Marco Kraemer ,  Carsten Otte ,  Christoph Raisch

    IPC: G06F12/12 ,  G06F12/10

    CPC classification number: G06F12/122 ,  G06F9/5077 ,  G06F9/52 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/123 ,  G06F12/1425 ,  G06F12/1466 ,  G06F12/1483 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/621 ,  G06F2212/657

    Abstract: A method for accessing data blocks stored in a computer system. The method may include hardware components for controlling access to a memory unit of the computer system. The memory unit includes a page table and an operating system, where each data block of the data blocks is accessed via a virtual address. The method further includes: adding an entry in the page table for each data block of a first set of the data blocks, the page table represents the virtual address; checking that a first entry of the added entries represents a first virtual address, in response to receiving a request of a first data block via the first virtual address by a memory management unit of the computer system; and obtaining a first physical address of the first data block from the hardware components, and the added entry is provided without indication of the first physical address.

    Abstract translation: 一种用于访问存储在计算机系统中的数据块的方法。 该方法可以包括用于控制对计算机系统的存储器单元的访问的硬件组件。 存储单元包括页表和操作系统，其中通过虚拟地址访问数据块的每个数据块。 该方法还包括：在第一组数据块的每个数据块的页表中添加条目，页表表示虚拟地址; 响应于所述计算机系统的存储器管理单元经由所述第一虚拟地址接收到第一数据块的请求，检查所添加的条目的第一条目是否表示第一虚拟地址; 以及从所述硬件组件获得所述第一数据块的第一物理地址，并且提供所述添加的条目而不指示所述第一物理地址。

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