公开(公告)号：US06787864B2

公开(公告)日：2004-09-07

申请号：US10335492

申请日：2002-12-31

申请人： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

发明人： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

IPC分类号： H01L2972

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66795 ,  H01L2029/7858

摘要： A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

公开(公告)号：US06764908B1

公开(公告)日：2004-07-20

申请号：US10173770

申请日：2002-06-19

申请人： Daniel Kadosh ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

发明人： Daniel Kadosh ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

IPC分类号： H01L21336

CPC分类号： H01L29/1054 ,  H01L21/823807

摘要： A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer. Embodiments include CMOS devices formed in substrates including a strained Si layer lattice-matched to a graded composition Si—Ge layer, wherein the thickness of the strained Si layer of each of the PMOS and NMOS transistors is adjusted to provide each transistor type with maximum drive current.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：（a）提供包括上部，拉伸应变晶格半导体层和下部未应力半导体层的半导体衬底; 和（b）在拉伸应变晶格半导体层上或其内形成至少一个MOS晶体管，其中所述形成包括通过调整拉伸应变晶格半导体层的厚度来调节所述至少一个MOS晶体管的驱动电流的步骤。 实施例包括形成在包括与渐变组合物Si-Ge层晶格匹配的应变Si层的衬底中的CMOS器件，其中调节每个PMOS晶体管和NMOS晶体管的应变Si层的厚度以提供每个晶体管类型的最大驱动 当前。

公开(公告)号：US06756276B1

公开(公告)日：2004-06-29

申请号：US10335522

申请日：2002-12-31

申请人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

发明人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

IPC分类号： H01L21336

CPC分类号： H01L29/66477 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.

摘要翻译： 在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。 形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。 第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。 通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。

公开(公告)号：US06737337B1

公开(公告)日：2004-05-18

申请号：US10134972

申请日：2002-04-29

申请人： Simon Siu-Sing Chan ,  Qi Xiang

发明人： Simon Siu-Sing Chan ,  Qi Xiang

IPC分类号： H01L2130

CPC分类号： H01L21/76254

摘要： A method of manufacturing a semiconductor device includes forming a buried insulator layer of a semiconductor-on-insulator (SOI) wafer with a dopant material, such as boron, therein. The insulator material with the dopant material may be formed by a number of methods, for example by thermal oxidation of a semiconductor wafer in the presence of an atmosphere containing the dopant material, by co-deposition of the insulator material and the dopant material, or by co-implantation of an insulator material and the dopant material. The dopant material may be the same as a dopant material in at least a region (e.g., a source, drain, or channel region) of a semiconductor material layer which overlies the insulator layer. The dopant material in the buried insulator layer may advantageously reduce the tendency of dopant material to migrate from the overlying material to the insulator layer, such as during manufacturing operations involving heating.

摘要翻译： 一种制造半导体器件的方法包括在其中用诸如硼的掺杂剂材料形成绝缘体上半导体（SOI）晶片的掩埋绝缘体层。 具有掺杂剂材料的绝缘体材料可以通过多种方法形成，例如通过在包含掺杂剂材料的气氛存在的情况下通过半导体晶片的热氧化，通过绝缘体材料和掺杂剂材料的共沉积，或 通过共注入绝缘体材料和掺杂剂材料。 掺杂剂材料可以与至少覆盖绝缘体层的半导体材料层的区域（例如，源极，漏极或沟道区）中的掺杂剂材料相同。 掩埋绝缘体层中的掺杂剂材料可以有利地降低掺杂剂材料从覆盖材料迁移到绝缘体层的趋势，例如在涉及加热的制造操作期间。

公开(公告)号：US06727534B1

公开(公告)日：2004-04-27

申请号：US10022847

申请日：2001-12-20

申请人： James F. Buller ,  Qi Xiang ,  Derick J. Wristers

发明人： James F. Buller ,  Qi Xiang ,  Derick J. Wristers

IPC分类号： H01L2979

CPC分类号： H01L29/4983 ,  H01L29/42376 ,  H01L29/66484 ,  H01L29/6656

摘要： High-speed MOS transistors are provided by forming a conductive layer embedded in transistor gate sidewall spacers. The embedded conductive layer is electrically insulated from the gate electrode and the source/drain regions of the transistor. The embedded conductive layer is positioned over the source/drain extensions and causes charge to accumulate in the source/drain extensions lowering the series resistance of the source/drain regions.

摘要翻译： 通过形成嵌入在晶体管栅极侧壁间隔物中的导电层来提供高速MOS晶体管。 嵌入式导电层与晶体管的栅极电极和源极/漏极区域电绝缘。 嵌入的导电层位于源极/漏极延伸部分上方，并使电荷累积在源极/漏极延伸部中，从而降低源极/漏极区域的串联电阻。

公开(公告)号：US06680250B1

公开(公告)日：2004-01-20

申请号：US10145740

申请日：2002-05-16

申请人： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

发明人： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC分类号： H01L2144

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268

摘要： A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain regions in the substrate extending to a first depth significantly greater than the intended junction depth. The amorphized source/drain regions are implanted with source/drain dopants such that the dopants extend into the substrate to a second depth less than the first depth, above and spaced apart from the end-of-range defect region created at the first depth by the amorphization process. Laser thermal annealing recrystallizes the amorphous regions, activates the source/drain regions and forms source/drain junctions. Because the recrystallization front velocity towards the substrate main surface is greater than the dopant atom velocity in the liquid substrate during laser thermal annealing, the junctions are not pushed down to the amorphous/crystalline silicon interface. Thus, end-of-range defects are located in a region below and spaced apart from the junctions, and the defects are not located in the activated source/drain regions. Junction leakage as a result of the end-of-range defects is thereby reduced.

摘要翻译： 一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间在衬底上形成栅极电极和栅极氧化物。 然后将惰性掺杂剂注入衬底内以在衬底中形成非晶化的源极/漏极区域，延伸到明显大于预期结点深度的第一深度。 非晶化源极/漏极区域注入源极/漏极掺杂剂，使得掺杂剂延伸到衬底中的第二深度小于第一深度的第二深度，在第一深度之上，并且与在第一深度处产生的端部范围缺陷区域间隔开 非晶化过程。 激光热退火使非晶区再结晶，激活源极/漏极区并形成源极/漏极结。 因为朝向衬底主表面的再结晶前向速度大于激光热退火期间液体衬底中的掺杂剂原子速度，所以接合点不被推到非晶/硅晶界面。 因此，距离范围缺陷位于与接合点下方和间隔开的区域中，并且缺陷不位于活化的源极/漏极区域中。 因此，由于距离范围缺陷导致的结漏电减少。

公开(公告)号：US06657276B1

公开(公告)日：2003-12-02

申请号：US10163925

申请日：2002-06-06

申请人： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

发明人： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

IPC分类号： H01L2900

CPC分类号： H01L29/7842 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

摘要翻译： 形成在半导体材料层中的浅沟槽隔离区。 浅沟槽隔离区域包括形成在半导体材料层中的沟槽，沟槽由侧壁和底部限定; 由高K材料形成的沟槽内的衬垫，衬垫符合沟槽的侧壁和底部; 以及由隔离材料制成并填充并符合高K衬里的填充部分。 还公开了形成浅沟槽隔离区域的方法。

公开(公告)号：US06600170B1

公开(公告)日：2003-07-29

申请号：US10015808

申请日：2001-12-17

申请人： Qi Xiang

发明人： Qi Xiang

IPC分类号： H01L2906

CPC分类号： H01L21/823807 ,  H01L27/092

摘要： Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.

摘要翻译： 由于PMOS晶体管中的空穴的迁移率小于NMOS晶体管中的电子的迁移率，所以传统的CMOS器件遭受不平衡。 由于应变硅提供比空穴迁移率更大的电子迁移率增加，在CMOS器件的通道中使用应变硅进一步加剧了电子和空穴迁移率的差异。 然而，在应变硅层下面的SiGe层中的空穴迁移率增加。 因此，通过在NMOS晶体管中包括应变硅而不是在CMOS器件的PMOS晶体管中形成更平衡的高速CMOS器件。

公开(公告)号：US06583012B1

公开(公告)日：2003-06-24

申请号：US09781436

申请日：2001-02-13

申请人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

发明人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

IPC分类号： H01L218234

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/28518 ,  H01L21/823842

摘要： MOS transistor and CMOS devices comprising a plurality of transistors including in-laid, metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal filling openings in an insulative layer at the bottom of which openings gate insulator layer segments of MOS transistor precursor regions formed in a semiconductor substrate are exposed; selectively forming at least one masking layer segment on the first blanket layer overlying selected ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or silicon over the thus-formed structure, and effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying other ones of the MOS transistor precursor regions. Unnecessary layers remaining after alloying or silicidation reaction are then removed by performing planarization processing, e.g., by CMP. The invention also includes MOS and CMOS devices comprising differently composed in-laid, metal-based gate electrodes.

摘要翻译： 包括多个晶体管的MOS晶体管和CMOS器件包括具有不同组成的嵌入式金属基栅极的多个晶体管，其特征在于，包括：在绝缘层的底部沉积第一金属填充开口的第一覆盖层， 形成在半导体衬底中的MOS晶体管前体区的开口栅极绝缘体层段露出; 选择性地形成覆盖所选择的MOS晶体管前体区域的第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或硅的第二覆盖层，并且在覆盖其它MOS晶体管前体区域的第一和第二覆盖层的接触部分之间进行合金化或硅化反应。 然后通过进行平坦化处理，例如通过CMP除去在合金化或硅化反应之后残留的不必要的层。 本发明还包括包括不同组合的嵌入式金属基栅极的MOS和CMOS器件。

公开(公告)号：US06562717B1

公开(公告)日：2003-05-13

申请号：US09679874

申请日：2000-10-05

申请人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

发明人： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

IPC分类号： H01L2144

CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/66545

摘要： A method of manufacturing a semiconductor device includes providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; and forming first and second nickel silicide layer respectively disposed on the source/drain regions and the gate electrode. The nickel silicide layer over the gate electrode can be thicker than the nickel silicide layer over the source/drain regions. A semiconductor device formed from the method is also disclosed.

摘要翻译： 一种制造半导体器件的方法包括：在具有源极/漏极区域的衬底上提供具有第一和第二相对侧壁的栅电极; 形成分别设置在所述第一和第二侧壁附近的第一和第二侧壁间隔件; 以及形成分别设置在源极/漏极区域和栅极电极上的第一和第二硅化镍层。 栅电极上的硅化镍层可以比源/漏区上的硅化镍层厚。 还公开了由该方法形成的半导体器件。