公开(公告)号：US08045412B2

公开(公告)日：2011-10-25

申请号：US12487165

申请日：2009-06-18

申请人： Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Andrew John Carter ,  Daniel Reed

发明人： Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Andrew John Carter ,  Daniel Reed

IPC分类号： G11C7/00

CPC分类号： G11C13/0064 ,  G11C11/1675 ,  G11C11/56 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2213/79

摘要： Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.

摘要翻译： 用于将数据传送到存储器的装置和相关方法，例如电阻读出存储器（RSM）。 根据一些实施例，包括逻辑状态序列的输入数据通过在第一写入步骤期间同时向第一多个单位单元中的每个单元写入第一逻辑状态而将第一逻辑状态写入存储器块，并且同时写入 在第二写入步骤期间从序列到第二非重叠多个单位单元中的每一个的第二逻辑状态。

公开(公告)号：US20110228598A1

公开(公告)日：2011-09-22

申请号：US13149136

申请日：2011-05-31

申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

IPC分类号： G11C11/14

CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  Y10S977/935

摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

摘要翻译： 描述基于传输门的自旋转移转矩存储单元。 存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。 磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

公开(公告)号：US20110205788A1

公开(公告)日：2011-08-25

申请号：US13100953

申请日：2011-05-04

申请人： Daniel Seymour Reed ,  Yong Lu ,  Song S. Xue ,  Dimitar V. Dimitrov ,  Paul E. Anderson

发明人： Daniel Seymour Reed ,  Yong Lu ,  Song S. Xue ,  Dimitar V. Dimitrov ,  Paul E. Anderson

IPC分类号： G11C11/15

CPC分类号： H01F10/329 ,  B82Y25/00 ,  G01R33/098 ,  G01R33/1284 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/3254

摘要： Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.

摘要翻译： 用于使用单向写入电流来存储非易失性存储器单元（诸如修改的STRAM单元）中的不同逻辑状态的方法和装置。 在一些实施例中，存储器单元具有与包层导体相邻的未固定的铁磁参考层，铁磁存储层和参考层与存储层之间的隧道势垒。 沿着包层导体的电流的通过在参考层中引入选定的磁取向，该参考层通过隧道势垒传递，以通过存储层进行存储。 此外，施加步骤的取向由邻近导体的包层提供，电流通过该导体，并且电流在所选择的磁方向的包层中感应出磁场。

公开(公告)号：US07974119B2

公开(公告)日：2011-07-05

申请号：US12170549

申请日：2008-07-10

申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

IPC分类号： G11C11/00

CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  Y10S977/935

摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

摘要翻译： 描述基于传输门的自旋转移转矩存储单元。 存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。 磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

公开(公告)号：US07881096B2

公开(公告)日：2011-02-01

申请号：US12408996

申请日：2009-03-23

申请人： Wenzhong Zhu ,  Yong Lu ,  Xiaobin Wang ,  Yiran Chen ,  Alan Xuguang Wang ,  Xiaohua Lou ,  Haiwen Xi

发明人： Wenzhong Zhu ,  Yong Lu ,  Xiaobin Wang ,  Yiran Chen ,  Alan Xuguang Wang ,  Xiaohua Lou ,  Haiwen Xi

IPC分类号： G11C17/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675

摘要： An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

摘要翻译： 一种用于补偿非易失性单元中不对称写入电流的装置和方法。 单位单元包括开关装置和非对称电阻感测元件（RSE），诸如非对称电阻随机存取存储器（RRAM）元件或非对称自旋转矩传递随机存取存储器（STRAM）元件。 RSE相对于开关装置在物理上定位在单位单元内，使得用于编程RSE的硬方向与单元单元的简单编程方向对齐，并且用于编程RSE的简单方向与硬方向对齐 编程单元格

公开(公告)号：US07876604B2

公开(公告)日：2011-01-25

申请号：US12390006

申请日：2009-02-20

申请人： Yuankai Zheng ,  Yiran Chen ,  Xiaobin Wang ,  Zheng Gao ,  Dimitar V. Dimitrov ,  Wenzhong Zhu ,  Yong Lu

发明人： Yuankai Zheng ,  Yiran Chen ,  Xiaobin Wang ,  Zheng Gao ,  Dimitar V. Dimitrov ,  Wenzhong Zhu ,  Yong Lu

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C11/1673

摘要： Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.

摘要翻译： 公开了自参考读取磁隧道结数据单元方法。 一种说明性方法包括在磁性隧道结数据单元上施加读取电压并形成读取电流。 磁性隧道结数据单元具有第一电阻状态。 读取电压足以切换磁性隧道结数据单元电阻。 该方法包括检测读取电流并确定在施加步骤期间读取电流是否保持恒定。 如果在施加步骤期间读取电流保持恒定，则磁性隧道结数据单元的第一电阻状态是读取电压足以将磁性隧道结数据单元切换到的电阻状态。

公开(公告)号：US20100302849A1

公开(公告)日：2010-12-02

申请号：US12474463

申请日：2009-05-29

申请人： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

发明人： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

IPC分类号： G11C14/00 ,  G11C16/04

CPC分类号： G11C11/005 ,  G11C16/26 ,  G11C2216/14

摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.

摘要翻译： 用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。 根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。 在一些实施例中，易失性存储器单元是来自所述单元的行的动态随机存取存储器（DRAM）单元，其中每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元 包括以NAND配置连接的闪存单元。

公开(公告)号：US07830726B2

公开(公告)日：2010-11-09

申请号：US12242590

申请日：2008-09-30

申请人： Henry F. Huang ,  Hai (Helen) Li ,  Yong Lu

发明人： Henry F. Huang ,  Hai (Helen) Li ,  Yong Lu

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C7/1006 ,  G11C7/1009 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/00 ,  G11C13/0004 ,  G11C2013/0076

摘要： Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.

摘要翻译： 使用读取 - 写入操作将数据写入存储阵列（例如但不限于STRAM或RRAM存储器阵列）的方法和装置。 根据各种实施例，读取存储在多个存储单元中的第一位模式。 第二位模式通过施加掩模来存储到多个存储器单元，以仅选择性地仅写入在第一和第二位模式之间对应于不同位值的所述多个存储单元。

公开(公告)号：US20100177562A1

公开(公告)日：2010-07-15

申请号：US12352713

申请日：2009-01-13

申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

IPC分类号： G11C11/14 ,  G11C7/00

CPC分类号： G11C11/22

摘要： Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.

摘要翻译： 各种实施例通常涉及与操作具有多个接口和状态寄存器的第一存储器件相关联的方法和装置。 在一些实施例中，主机接合第一接口。 具有由至少磁性隧道结和自旋极化磁性材料构成的多个存储单元的存储器件连接到第二接口。 通过在数据传输操作期间通过第一和第二接口记录至少一个错误或忙信号来维护状态寄存器。

公开(公告)号：US20100177554A1

公开(公告)日：2010-07-15

申请号：US12502211

申请日：2009-07-13

申请人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

发明人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

IPC分类号： G11C11/00 ,  G11C11/14

CPC分类号： G11C13/0004 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/76

摘要： A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.

摘要翻译： 电阻式感测存储装置包括具有半导体衬底和设置在半导体衬底中并形成行或晶体管的多个晶体管的双极选择器件。 每个晶体管包括发射极触点和集电极触点。 每个集电极触点彼此电隔离，并且每个发射极触点彼此电隔离。 栅极触点沿发射极触点和集电极触点之间的沟道区域延伸。 基极触点设置在半导体衬底内，使得发射极触点和集电极触点位于栅极触点和基极触点之间。 电阻读出存储单元电耦合到每个集电极触点或发射极触点和位线。