公开(公告)号：US20060081932A1

公开(公告)日：2006-04-20

申请号：US11292911

申请日：2005-12-01

申请人： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

发明人： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

公开(公告)号：US20060065939A1

公开(公告)日：2006-03-30

申请号：US10951073

申请日：2004-09-27

申请人： Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

发明人： Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC分类号： H01L29/94 ,  H01L21/3205

CPC分类号： H01L21/823437 ,  H01L21/823828

摘要： A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.

摘要翻译： 互补金属氧化物半导体集成电路可以形成有在半导体衬底上具有高介电常数栅极电介质材料的NMOS和PMOS晶体管。 可以在栅极电介质上方形成金属阻挡层。 在金属阻挡层上方形成功函设定金属层，在功函设定金属层上形成帽金属层。

公开(公告)号：US20060063318A1

公开(公告)日：2006-03-23

申请号：US10938778

申请日：2004-09-10

申请人： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Marko Radosavljevic ,  Amlan Majumdar ,  Justin Brask ,  Robert Chau

发明人： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Marko Radosavljevic ,  Amlan Majumdar ,  Justin Brask ,  Robert Chau

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L51/102 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0545 ,  H01L51/105

摘要： Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.

摘要翻译： 通过形成金属的栅电极，可以在碳纳米管晶体管中减少双极传导。 可以形成具有与栅电极不同的功函数的金属侧壁间隔物以支撑金属栅电极。

公开(公告)号：US20060022271A1

公开(公告)日：2006-02-02

申请号：US10900585

申请日：2004-07-28

申请人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： H01L27/01

CPC分类号： H01L21/823462 ,  H01L21/823857

摘要： Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a subtractive process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.

公开(公告)号：US20060017122A1

公开(公告)日：2006-01-26

申请号：US11231437

申请日：2005-09-20

申请人： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

发明人： Robert Chau ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.

公开(公告)号：US20060006522A1

公开(公告)日：2006-01-12

申请号：US10889535

申请日：2004-07-12

申请人： Mark Doczy ,  Mitchell Taylor ,  Justin Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew Metz ,  Robert Chau ,  Jack Hwang

发明人： Mark Doczy ,  Mitchell Taylor ,  Justin Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew Metz ,  Robert Chau ,  Jack Hwang

IPC分类号： H01L23/14

CPC分类号： H01L21/823842

摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.

公开(公告)号：US20050287746A1

公开(公告)日：2005-12-29

申请号：US10877232

申请日：2004-06-24

申请人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/517 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772

摘要： In a metal gate replacement process, a gate electrode stack may be formed of a germanium containing layer. In subsequent processing of the source/drains, high temperature steps may be utilized, forming a germinide on said stacks. That germinide may be removed, prior to removing the rest of the stack, using H2O2.

摘要翻译： 在金属栅极替换工艺中，栅电极堆叠可以由含锗层形成。 在源/下水道的后续处理中，可以利用高温步骤，在所述堆上形成发芽。 在使用H 2 O 2 O 2除去堆叠的其余部分之前，可以除去该发芽物。

公开(公告)号：US20050280050A1

公开(公告)日：2005-12-22

申请号：US11202541

申请日：2005-08-11

申请人： Mark Doczy ,  Nathan Baxter ,  Robert Chau ,  Kari Harkonen ,  Teemu Lang

发明人： Mark Doczy ,  Nathan Baxter ,  Robert Chau ,  Kari Harkonen ,  Teemu Lang

IPC分类号： C22C32/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L27/148 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/768

CPC分类号： H01L29/4966 ,  C04B35/5618 ,  C04B2235/722 ,  C04B2235/723 ,  C22C14/00 ,  C22C16/00 ,  C22C27/00 ,  C22C32/0084 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/6659

摘要： Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.

公开(公告)号：US20050224886A1

公开(公告)日：2005-10-13

申请号：US10816232

申请日：2004-03-31

申请人： Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Robert Chau

发明人： Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Robert Chau

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L29/4983 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/32051 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

摘要： A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.

公开(公告)号：US20050202644A1

公开(公告)日：2005-09-15

申请号：US11120353

申请日：2005-05-02

申请人： Mark Doczy ,  Mark Liu ,  Jack Kavalieros ,  Justin Brask ,  Matthew Metz ,  Robert Chau

发明人： Mark Doczy ,  Mark Liu ,  Jack Kavalieros ,  Justin Brask ,  Matthew Metz ,  Robert Chau

IPC分类号： H01L21/268 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/495 ,  H01L21/268 ,  H01L21/823828 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/6659

摘要： Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.

摘要翻译： 描述形成微电子结构的方法。 这些方法包括提供包括源极/漏极和栅极区域的衬底，其中栅极区域包括设置在栅极介电层上的金属层，然后激光退火衬底。