公开(公告)号：US07119443B2

公开(公告)日：2006-10-10

申请号：US10959634

申请日：2004-10-07

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

摘要翻译： 根据以下步骤形成半导体器件。 通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀 仅留下通孔66的内部并形成插头73。 然后，通过溅射法将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，然后，将Ti膜76，Al合金膜75， 并且将TiN膜74图案化以形成第二层布线77和78。

公开(公告)号：US20050282335A1

公开(公告)日：2005-12-22

申请号：US11153321

申请日：2005-06-16

申请人： Kensuke Okonogi ,  Kiyonori Ohyu ,  Kazutaka Manabe ,  Satoru Yamada ,  Takuo Ohashi

发明人： Kensuke Okonogi ,  Kiyonori Ohyu ,  Kazutaka Manabe ,  Satoru Yamada ,  Takuo Ohashi

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76877 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66575

摘要： A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.

摘要翻译： 在硅衬底上制造DRAM器件的方法包括：在存储单元区域中形成单元晶体管和外围电路区域中的其它晶体管; 形成连接到所述单元晶体管的扩散区域的多晶硅插塞和连接到所述另一晶体管的扩散区域的金属插塞; 在980〜1020℃的温度下进行热处理。 在700〜850℃的温度下进行热处理。 将氟或氟化硼注入其他晶体管的扩散区域; 并在500〜850℃的温度下进行热处理。

公开(公告)号：US20050208716A1

公开(公告)日：2005-09-22

申请号：US11130236

申请日：2005-05-17

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/49

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823857 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L29/4941 ,  H01L29/6656

摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。 存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。 通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。 此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。 结果，可以以自对准的方式降低硼渗透并形成接触电极。 此外，可以提高构成逻辑电路的MISFET的性能。

公开(公告)号：US06853081B2

公开(公告)日：2005-02-08

申请号：US10453611

申请日：2003-06-04

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L23/48 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

摘要翻译： 根据以下步骤形成半导体器件。 通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀 仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过 溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

公开(公告)号：US20050000560A1

公开(公告)日：2005-01-06

申请号：US10876666

申请日：2004-06-28

申请人： Hidenori Shiotsuka ,  Ichiro Kataoka ,  Satoru Yamada ,  Shigeo Kiso ,  Hideaki Zenko

发明人： Hidenori Shiotsuka ,  Ichiro Kataoka ,  Satoru Yamada ,  Shigeo Kiso ,  Hideaki Zenko

IPC分类号： H01L31/042 ,  H01L31/0203 ,  H01L31/048 ,  H01L31/18 ,  H02N6/00

CPC分类号： H01L31/18 ,  H01L31/048 ,  Y02B10/12 ,  Y02E10/50 ,  Y02W30/827 ,  Y10S136/29

摘要： A solar cell module comprising a substrate, a filler, a photovoltaic element and a protective layer, wherein at least one of the substrate, the filler, the photovoltaic element and the protective layer is separable from other constituent members. Constituent members having been separated and still serviceable can be reused.

摘要翻译： 一种太阳能电池模块，包括基板，填料，光电元件和保护层，其中基板，填料，光电元件和保护层中的至少一个可与其它构成元件分离。 分离成员和仍然可维持的成员可以重复使用。

公开(公告)号：US06812540B2

公开(公告)日：2004-11-02

申请号：US10298682

申请日：2002-11-19

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L2900

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有源区域nwp1和nw1之间的宽度为L4，有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US06605530B2

公开(公告)日：2003-08-12

申请号：US10287616

申请日：2002-11-05

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L214763

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

公开(公告)号：US06356179B1

公开(公告)日：2002-03-12

申请号：US09506376

申请日：2000-02-18

申请人： Satoru Yamada

发明人： Satoru Yamada

IPC分类号： H01F1706

CPC分类号： H01F17/04

摘要： An inductance device according to the present invention, which is for use in power supply units, is constructed in such a manner that a slit 3 is provided in one side of a polygonal cylindrical ferrite core 1 in the same direction to a hollow portion 2 to form an open magnetic path, and a belt-like conductor 4 is inserted through the hollow portion 2, so as to minimize the dimensions, have an inductance value not more than 1 &mgr;H, and hold DC overlapping characteristic flat even if high current flows.

摘要翻译： 根据本发明的用于电力供应单元的电感装置的结构是这样一种方式，即在多边形圆柱形铁氧体磁芯1的一侧上设置有一个与中空部分2相同方向的狭缝3， 形成开放的磁路，并且通过中空部分2插入带状导体4，以使尺寸最小化，电感值不大于1μH，并且即使高电流流动，也保持DC重叠特性平坦。

公开(公告)号：US06249202B1

公开(公告)日：2001-06-19

申请号：US09472849

申请日：1999-12-28

申请人： Satoru Yamada

发明人： Satoru Yamada

IPC分类号： H01F2706

CPC分类号： H01F27/29 ,  H01F37/00

摘要： A plate-like coil formed by a metal plate is buried in a base made from an insulating material in a state in which electrode terminals and a fixing terminal of the plate-like coil are projecting from the base. The base has through-holes in which a central leg and side legs of an E-shaped core are to be inserted. The E-shaped core and an I-shaped core are mounted to the base while holding the base therebetween, and the electrode terminals and the fixing terminal projecting from the base are bent to the bottom surface of the base. Each of an electrode terminal bent portion located bottom surface portion at which the electrode terminals are to be disposed and a fixing terminal bent portion located bottom surface portion at which the fixing terminal is to be disposed is positioned upwardly from a base bottom portion, and a recessed groove is provided between the base bottom portion and each of the electrode terminal bent portion located bottom surface portion and the fixing terminal bent portion located bottom surface portion.

摘要翻译： 由金属板形成的板状线圈被埋在由绝缘材料制成的基座中，其中电极端子和板状线圈的固定端子从基座突出的状态。 基座具有插入E形芯的中心腿和侧腿的通孔。 E形芯和I形芯安装在基座上，同时保持基座，并且从基座突出的电极端子和固定端子弯曲到基座的底表面。 位于要设置电极端子的底表面部分的电极端子弯曲部分和位于要设置固定端子的底表面部分的固定端子弯曲部分位于基底部的上方，并且 在基底部和位于底面部分的电极端弯曲部分和位于底表面部分的固定端弯曲部分之间设置凹槽。

公开(公告)号：US5939164A

公开(公告)日：1999-08-17

申请号：US805301

申请日：1997-02-25

申请人： Yoshinari Kubo ,  Ken-ichi Ogura ,  Yoichiro Bekki ,  Satoru Yamada ,  Koji Kinoshita

发明人： Yoshinari Kubo ,  Ken-ichi Ogura ,  Yoichiro Bekki ,  Satoru Yamada ,  Koji Kinoshita

IPC分类号： B32B3/02 ,  B32B15/01 ,  B32B15/10

CPC分类号： B32B15/016 ,  Y10T428/12028 ,  Y10T428/12063 ,  Y10T428/12736 ,  Y10T428/12764

摘要： The present invention relates to an aluminum alloy for a magnetic disk substrate having a composition consisting of, by percent by weight, 2.0 to 6.0% of Mg, 0.05 to 0.15% of Cu, 0.10 to 0.30% of Zn and 0.05 to 0.12% of Zr, wherein the contents of Cu, Zn and Zr satisfy the relationship: 0.15%.ltoreq.2Cu+6Zr-3Zn.ltoreq.0.32% (wherein Cu, Zr, and Zn respectively represent their contents in terms of percent by weight), and the composition further consists of one or both of 0.01 or more to less than 0.05% of Cr and 0.01 or more to less than 0.05% of Mn, impurities consisting of Si, Fe and Ti, which are respectively regulated to be 0.05% or less, 0.05% or less, and 0.02% or less, and other inevitable impurity elements respectively regulated to be 0.02% or less, with the remainder being Al. The present invention also relates to a clad material for a magnetic disk substrate, in which one or both surfaces of a core material, consisting of at least less than 3.0% of Zn with the remainder being Al and inevitable impurity elements, are clad with a surface material consisting of the aluminum alloy having the above composition. The above aluminum alloy composition makes it possible to manufacture a large storage memory capacity magnetic disk in which there is much less formation of micropits or nodules.

摘要翻译： 本发明涉及一种磁盘基板用铝合金，其组成为以重量％计含有2.0〜6.0％的Mg，0.05〜0.15％的Cu，0.10〜0.30％的Zn和0.05〜0.12％的Zn Zr，其中Cu，Zn和Zr的含量满足关系：0.15％