公开(公告)号：US10269441B1

公开(公告)日：2019-04-23

申请号：US16049411

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  William C. Waldrop

IPC: G11C11/24 ,  G11C17/18 ,  H04L9/08 ,  G11C17/16 ,  G11C17/08

Abstract: A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.

公开(公告)号：US10127994B1

公开(公告)日：2018-11-13

申请号：US15789167

申请日：2017-10-20

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  William C. Waldrop

IPC: G11C11/24 ,  G11C17/18 ,  H04L9/08 ,  G11C17/16 ,  G11C17/08

Abstract: A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.

公开(公告)号：US20180114551A1

公开(公告)日：2018-04-26

申请号：US15797759

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata

IPC: G11C7/06 ,  H03K19/20

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/005 ,  H03K19/20

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

公开(公告)号：US20180108397A1

公开(公告)日：2018-04-19

申请号：US15292941

申请日：2016-10-13

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/408

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

公开(公告)号：US20180024926A1

公开(公告)日：2018-01-25

申请号：US15214982

申请日：2016-07-20

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F12/0815

CPC classification number: G06F12/0215 ,  G06F12/0859 ,  G06F13/16 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

公开(公告)号：US09767864B1

公开(公告)日：2017-09-19

申请号：US15216256

申请日：2016-07-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/10 ,  G11C7/22

CPC classification number: G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/222 ,  G11C8/10 ,  G11C11/403 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

公开(公告)号：US11854618B2

公开(公告)日：2023-12-26

申请号：US17446710

申请日：2021-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniel B. Penney ,  Jason M. Brown

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for determining extremum numerical values. Numerical values may be stored in files of a stack, with each bit of the numerical value stored in a content addressable memory (CAM) cell of the file. Each file may be associated with an accumulator circuit, which provides an accumulator signal. An extremum search operation may be performed where a sequence of comparison bits are compared in a bit-by-bit fashion to each bit of the numerical values. The accumulator circuits each provide an accumulator signal which indicates if the numerical value in the associated file is an extremum value or not. Examples of extremum search operations include finding a maximum of the numerical values and a minimum of the numerical values.

公开(公告)号：US11495281B2

公开(公告)日：2022-11-08

申请号：US16834409

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： William C. Waldrop ,  Daniel B. Penney

IPC: G11C11/00 ,  G11C11/4076 ,  G06F11/10 ,  G11C11/4096 ,  G11C11/4093

Abstract: Systems and methods are provided that provide protection from undesired latching that may be caused by indeterminate interamble periods in an input/output data strobe (DQS) signal. Interamble compensation circuitry selectively filters out interamble states of the DQS signal to reduce provision of interamble signals to downstream components that use the DQS signal to identify data latching times.

公开(公告)号：US11145353B1

公开(公告)日：2021-10-12

申请号：US16844182

申请日：2020-04-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William Chad Waldrop ,  Daniel B. Penney

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  H04L25/03

Abstract: Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.

公开(公告)号：US20210241805A1

公开(公告)日：2021-08-05

申请号：US16779866

申请日：2020-02-03

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.