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    DYNAMIC BACKGROUND SCAN OPTIMIZATION IN A MEMORY SUB-SYSTEM
    101.
    发明申请
    DYNAMIC BACKGROUND SCAN OPTIMIZATION IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220350538A1

    公开(公告)日：2022-11-03

    申请号：US17865686

    申请日：2022-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Gerald L. Cadloni ,  Michael Sheperek ,  Francis Chew ,  Bruce A. Liikanen ,  Larry J. Koudele

    IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F13/42 ,  G06F13/16

    Abstract: Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

    ADJUSTMENT OF A STARTING VOLTAGE CORRESPONDING TO A PROGRAM OPERATION IN A MEMORY SUB-SYSTEM
    102.
    发明申请
    ADJUSTMENT OF A STARTING VOLTAGE CORRESPONDING TO A PROGRAM OPERATION IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220343981A1

    公开(公告)日：2022-10-27

    申请号：US17861467

    申请日：2022-07-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Bruce A. Liikanen ,  Michael Sheperek ,  Larry J. Koudele

    IPC: G11C16/10 ,  G06F3/06

    Abstract: A processing device determines a measured bit error count (BEC) value corresponding to a read sample offset operation executed on a first programming voltage distribution of memory cells of a plurality of programming voltage distributions of a memory sub-system. The measured BEC value of the portion of the programming voltage distribution is compared to a threshold BEC value to generate a comparison result. In view of the comparison result, an adjusted program start voltage level is determined by adjusting a default program voltage level of a programming process. The programming process including a series of programming pulses is executed, where the adjusted program start voltage level is set as a starting voltage level of a first programming pulse of the series of programming pulses.

    Error avoidance based on voltage distribution parameters of block families
    104.
    发明授权
    Error avoidance based on voltage distribution parameters of block families 有权

    公开(公告)号：US11443830B1

    公开(公告)日：2022-09-13

    申请号：US17217780

    申请日：2021-03-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Michael Sheperek ,  Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N Kaynak ,  Larry J Koudele

    IPC: G11C29/56 ,  G11C16/26

    Abstract: A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a first data structure mapping block identifiers to corresponding block family identifiers, a block family associated with the block of the memory device, determining, using a second data structure mapping block family identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block family, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device, and reading, using the determined set of read levels, data from the block of the memory device.

    Closing block family based on soft and hard closure criteria
    105.
    发明授权
    Closing block family based on soft and hard closure criteria 有权

    公开(公告)号：US11429504B2

    公开(公告)日：2022-08-30

    申请号：US16947712

    申请日：2020-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Michael Sheperek ,  Larry J. Koudele ,  Steven S. Williams

    IPC: G06F11/30 ,  G06F11/07 ,  G06F3/06 ,  G06F11/10 ,  G06F11/16

    Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations, including initializing a block family associated with the memory device and initializing a timer associated with the block family. Responsive to beginning to program a block residing on the memory device, the processing device associates the block with the block family. In response to the timer reaching a soft closure value, the processing device performs a soft closure of the block family; continues to program data to the block; and performs a hard closure of the block family in response to one of the timer reaching a hard closure value or the block family satisfying a hard closure criteria.

    WRITE DATA FOR BIN RESYNCHRONIZATION AFTER POWER LOSS
    106.
    发明申请
    WRITE DATA FOR BIN RESYNCHRONIZATION AFTER POWER LOSS 有权

    公开(公告)号：US20220197795A1

    公开(公告)日：2022-06-23

    申请号：US17694434

    申请日：2022-03-14

    Applicant: Micron Technology, Inc.

    Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Steven Michael Kientz

    IPC: G06F12/0804 ,  G06F3/06 ,  G11C16/30 ,  G11C16/32 ,  G01R19/165 ,  G11C16/10

    Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device, the processing device to perform operations comprising: measuring one of a temperature voltage shift or a read bit error rate of fixed data stored in the memory device in response to detecting a power on of the memory device, the fixed data having been programmed in response to detecting a power loss; estimating an amount of time for which the memory device was powered off based on results of the measuring; and in response to the amount of time satisfying a threshold criterion, updating a value for a temporal voltage shift of a block family based on the amount of time.

    TIME-BASED COMBINING FOR BLOCK FAMILIES OF A MEMORY DEVICE
    110.
    发明申请
    TIME-BASED COMBINING FOR BLOCK FAMILIES OF A MEMORY DEVICE 有权

    公开(公告)号：US20220164106A1

    公开(公告)日：2022-05-26

    申请号：US17100712

    申请日：2020-11-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shane Nowell ,  Michael Sheperek ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

    IPC: G06F3/06

    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to determine that a first block family of a plurality of block families of the memory device and a second block family of the plurality of block families satisfy a proximity condition; determine whether the first block family and the second block family meet a time-based combining criterion corresponding to the proximity condition; and responsive to determining that the first block family and the second block family meet the time-based combining criterion, merge the first block family and the second block family.

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