公开(公告)号：US06756814B2

公开(公告)日：2004-06-29

申请号：US10345242

申请日：2003-01-16

申请人： Yoshikazu Saitou ,  Kenichi Osada

发明人： Yoshikazu Saitou ,  Kenichi Osada

IPC分类号： H03K19175

CPC分类号： H03K19/0016

摘要： The present invention is directed to simplify a circuit for fixing an output logic of a logic gate while suppressing a subthreshold current. A logic circuit has an n-channel type first transistor capable of interrupting power supply to a logic gate in accordance with an input control signal, and a p-channel type second transistor capable of fixing an output node of the logic gate to a high level interlockingly with the power supply interrupting operation by the first transistor, and a threshold of the first transistor is set to be higher than that of a transistor as a component of the logic gate. Means for interrupting the power supply to the logic gate is realized by the first transistor, and means for fixing an output node of the logic gate to the high level is realized by the second transistor, thereby simplifying the circuit for fixing the output logic of the logic gate while suppressing a subthreshold current.

摘要翻译： 本发明旨在简化用于在抑制亚阈值电流的同时固定逻辑门的输出逻辑的电路。 逻辑电路具有能够根据输入控制信号中断到逻辑门的电源的n沟道型第一晶体管，以及能够将逻辑门的输出节点固定为高电平的p沟道型第二晶体管 与第一晶体管的电源中断操作互锁，并且将第一晶体管的阈值设置为高于作为逻辑门的组件的晶体管的阈值。 用于中断对逻辑门的电源的装置由第一晶体管实现，并且通过第二晶体管实现将逻辑门的输出节点固定为高电平的装置，从而简化用于固定逻辑门的输出逻辑的电路 同时抑制亚阈值电流。

公开(公告)号：US06559006B2

公开(公告)日：2003-05-06

申请号：US10157978

申请日：2002-05-31

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L218242

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质 介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

公开(公告)号：US06525985B2

公开(公告)日：2003-02-25

申请号：US09577366

申请日：2000-05-23

申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

IPC分类号： G11C514

CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02D10/13

摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

公开(公告)号：US06515894B2

公开(公告)日：2003-02-04

申请号：US09988197

申请日：2001-11-19

申请人： Kenichi Osada ,  Hisayuki Higuchi ,  Koichiro Ishibashi

发明人： Kenichi Osada ,  Hisayuki Higuchi ,  Koichiro Ishibashi

IPC分类号： G11C1100

CPC分类号： G11C7/18 ,  G06F12/0802 ,  G11C7/065

摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

公开(公告)号：US06436753B1

公开(公告)日：2002-08-20

申请号：US09372007

申请日：1999-08-11

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L218244

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，对于形成SRAM的存储单元的负载电阻QL的转移MISFET Qt和MISFET相对有意地高于诸如微处理器的SRAM外围电路和逻辑电路的预定MISFET的Vth， 引入杂质引入步骤，用于设置用于设置预定MISFET的Vth的杂质引入步骤的驱动MISFET Qd，负载电阻的转移MISFET Qt和MISFET的Vth。

公开(公告)号：US06396732B1

公开(公告)日：2002-05-28

申请号：US09577149

申请日：2000-05-24

申请人： Kenichi Osada ,  Hisayuki Higuchi ,  Koichiro Ishibashi

发明人： Kenichi Osada ,  Hisayuki Higuchi ,  Koichiro Ishibashi

IPC分类号： G11C1100

CPC分类号： G11C7/18 ,  G06F12/0802 ,  G11C7/065

摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

公开(公告)号：US06295218B1

公开(公告)日：2001-09-25

申请号：US09549230

申请日：2000-04-13

申请人： Kenichi Osada ,  Koichiro Ishibashi

发明人： Kenichi Osada ,  Koichiro Ishibashi

IPC分类号： G11C1500

CPC分类号： G06F12/1027 ,  G06F12/0864 ,  G11C15/00 ,  G11C15/04

摘要： A memory device having a plurality of blocks, each of a plurality of blocks comprising a memory array having a plurality of word lines and a plurality of memory cells connected to the word lines, an associative cell array for outputting a hit signal by comparing a first address inputted thereto with internal data and a decoder circuit for selecting one line by decoding a second address and wherein one of the word lines is selected based on the line selected by the decoder circuit and the hit signal.

摘要翻译： 一种存储器件，具有多个块，多个块中的每一个包括具有多个字线的存储器阵列和连接到所述字线的多个存储器单元;相关单元阵列，用于通过比较第一 用内部数据输入的地址，以及通过解码第二地址来选择一行的解码器电路，并且其中基于由解码器电路选择的行和命中信号来选择一个字线。

公开(公告)号：US06212117B1

公开(公告)日：2001-04-03

申请号：US09588831

申请日：2000-06-07

申请人： Jin-Uk Luke Shin ,  Kenichi Osada ,  Masood Khan

发明人： Jin-Uk Luke Shin ,  Kenichi Osada ,  Masood Khan

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C7/1072 ,  G11C7/22

摘要： A CMOS memory array, including a number of bit cells arranged in an array of N rows and M columns includes a duplicate column of bit cells that is used for self-timing. Receipt of an address will access a predetermined number of the bit cells to generate a reset signal that is used to enable sense amplifiers for sampling bit lines of the array.

摘要翻译： CMOS存储器阵列包括以N行和M列阵列排列的多个位单元，包括用于自定时的位单元的重复列。 接收地址将访问预定数量的比特单元以产生用于使读出放大器对阵列的位线进行采样的复位信号。

公开(公告)号：US5943284A

公开(公告)日：1999-08-24

申请号：US705315

申请日：1996-08-29

申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

IPC分类号： G11C11/41 ,  G06F12/08 ,  G11C5/06 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02B60/1225

摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

公开(公告)号：US20190209081A1

公开(公告)日：2019-07-11

申请号：US16333602

申请日：2017-09-15

申请人： Kenichi Osada

发明人： Kenichi Osada

IPC分类号： A61B5/00 ,  A61B5/16

CPC分类号： A61B5/483 ,  A61B5/165 ,  A61B5/4827 ,  A61B5/7246 ,  A61B10/00

摘要： The present invention addresses the problem of providing a system and a method for noninvasively and conveniently diagnosing difficult-to-diagnose chronic pain-related diseases and/or diseases requiring differentiation from the chronic pain-related diseases. The problem was solved by providing a method for obtaining an indicator for determining the presence and/or type of a chronic pain-related disease and/or disease requiring differentiation from chronic pain-related diseases, the method comprising: (a) performing an offset measurement test of pain on a subject that does not suffer from a neurological disorder; (b) analyzing the results obtained from the test in (a); and (c) comparing the analysis results obtained in (b) with a reference value.